Raul E Rangel f87427f1a4 soc/amd/stoneyridge: Add SPI registers ... This is a copy/paste of amdblocks/lpc.h. The registers are different for picasso and cezanne, so I'm moving them to soc. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4dfadcdc025d3581cb1423e9793a9b2181742b9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/50443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>		2021-02-10 19:00:17 +00:00
..
cezanne	soc/amd/cezanne/chip: add empty set_mmio_dev_ops	2021-02-10 16:09:32 +00:00
common	soc/amd/common/block: Fix guards for PSP transfer buffer	2021-02-10 16:23:56 +00:00
picasso	soc/amd/picasso/smihandler: replace southbridge.c in comment with fch.c	2021-02-10 16:17:57 +00:00
stoneyridge	soc/amd/stoneyridge: Add SPI registers	2021-02-10 19:00:17 +00:00
Kconfig	soc/amd: rename common Kconfig and use wildcard for SoC-specific Kconfig	2020-11-19 14:29:14 +00:00