coreboot-kgpe-d16/src/southbridge/intel
Arthur Heymans 98c92570d9 cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm
C5, C6 and slfm depend on the southbridge and the northbridge to be able
to provide this functionality, with some just lacking the possibility to
do so. Move the devicetree configuration to the southbridge.

This removes the need for a magic lapic in the devicetree.

Change-Id: I4a9b1e684a7927259adae9b1d42a67e907722109
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-05 14:22:12 +00:00
..
bd82x6x /: Remove extra space after comma 2022-11-30 03:07:23 +00:00
common sb,soc/intel: Drop spurious SMI entry message 2022-11-28 10:26:27 +00:00
i82371eb treewide: use is_enabled_cpu() on cycles over device list 2022-09-29 16:47:04 +00:00
i82801dx sb,soc/intel: Apply transitional flag TCO_SPACE_NOT_YET_SPLIT 2022-11-28 10:08:23 +00:00
i82801gx cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm 2022-12-05 14:22:12 +00:00
i82801ix cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm 2022-12-05 14:22:12 +00:00
i82801jx cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm 2022-12-05 14:22:12 +00:00
i82870 sb/intel/i82870: Use register_new_ioapic() 2022-11-10 19:19:23 +00:00
ibexpeak sb,soc/intel: Apply transitional flag TCO_SPACE_NOT_YET_SPLIT 2022-11-28 10:08:23 +00:00
lynxpoint /: Remove extra space after comma 2022-11-30 03:07:23 +00:00