6b5bc77c9b
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
129 lines
3.4 KiB
C
129 lines
3.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_def.h>
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#include <device/pci_ops.h>
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#include <device/pciexp.h>
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#include <device/pci_ids.h>
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#include <southbridge/intel/common/pciehp.h>
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#include "chip.h"
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static void pci_init(struct device *dev)
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{
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u16 reg16;
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u32 reg32;
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struct southbridge_intel_i82801jx_config *config = dev->chip_info;
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printk(BIOS_DEBUG, "Initializing ICH10 PCIe root port.\n");
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/* Enable Bus Master */
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pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
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/* Set Cache Line Size to 0x10 */
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// This has no effect but the OS might expect it
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pci_write_config8(dev, 0x0c, 0x10);
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reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
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reg16 &= ~PCI_BRIDGE_CTL_PARITY;
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reg16 |= PCI_BRIDGE_CTL_NO_ISA;
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pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16);
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/* Enable IO xAPIC on this PCIe port */
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reg32 = pci_read_config32(dev, 0xd8);
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reg32 |= (1 << 7);
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pci_write_config32(dev, 0xd8, reg32);
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/* Enable Backbone Clock Gating */
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reg32 = pci_read_config32(dev, 0xe1);
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reg32 |= (1 << 3) | (1 << 2) | (1 << 1) | (1 << 0);
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pci_write_config32(dev, 0xe1, reg32);
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/* Set VC0 transaction class */
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reg32 = pci_read_config32(dev, 0x114);
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reg32 &= 0xffffff00;
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reg32 |= 1;
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pci_write_config32(dev, 0x114, reg32);
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/* Mask completion timeouts */
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reg32 = pci_read_config32(dev, 0x148);
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reg32 |= (1 << 14);
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pci_write_config32(dev, 0x148, reg32);
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/* Lock R/WO Correctable Error Mask. */
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pci_write_config32(dev, 0x154, pci_read_config32(dev, 0x154));
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/* Clear errors in status registers */
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reg16 = pci_read_config16(dev, 0x06);
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pci_write_config16(dev, 0x06, reg16);
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reg16 = pci_read_config16(dev, 0x1e);
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pci_write_config16(dev, 0x1e, reg16);
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/* Get configured ASPM state */
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const enum aspm_type apmc = pci_read_config32(dev, 0x50) & 3;
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/* If both L0s and L1 enabled then set root port 0xE8[1]=1 */
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if (apmc == PCIE_ASPM_BOTH) {
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reg32 = pci_read_config32(dev, 0xe8);
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reg32 |= (1 << 1);
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pci_write_config32(dev, 0xe8, reg32);
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}
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/* Enable expresscard hotplug events. */
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if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) {
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pci_write_config32(dev, 0xd8,
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pci_read_config32(dev, 0xd8)
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| (1 << 30));
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pci_write_config16(dev, 0x42, 0x142);
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}
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}
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static void pch_pciexp_scan_bridge(struct device *dev)
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{
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struct southbridge_intel_i82801jx_config *config = dev->chip_info;
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/* Normal PCIe Scan */
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pciexp_scan_bridge(dev);
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if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) {
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intel_acpi_pcie_hotplug_scan_slot(dev->link_list);
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}
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}
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static struct pci_operations pci_ops = {
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.set_subsystem = pci_dev_set_subsystem,
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};
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static struct device_operations device_ops = {
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.read_resources = pci_bus_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_bus_enable_resources,
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.init = pci_init,
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.scan_bus = pch_pciexp_scan_bridge,
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.ops_pci = &pci_ops,
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};
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/* 82801lJx, ICH10 */
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static const unsigned short pci_device_ids[] = {
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0x3a40, /* Port 1 */
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0x3a42, /* Port 2 */
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0x3a44, /* Port 3 */
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0x3a46, /* Port 4 */
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0x3a48, /* Port 5 */
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0x3a4a, /* Port 6 */
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0x3a70, /* Port 1 */
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0x3a72, /* Port 2 */
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0x3a74, /* Port 3 */
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0x3a76, /* Port 4 */
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0x3a78, /* Port 5 */
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0x3a7a, /* Port 6 */
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0
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};
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static const struct pci_driver ich10_pcie __pci_driver = {
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.ops = &device_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.devices = pci_device_ids,
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};
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