e56189cfd1
Move inline function where they belong to. Fixes compilation on non x86 platforms. Change-Id: Ia05391c43b8d501bd68df5654bcfb587f8786f71 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25720 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
40 lines
1.1 KiB
C
40 lines
1.1 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018 Advanced Micro Devices
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <soc/northbridge.h>
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#include <soc/pci_devs.h>
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#include <device/pci_ops.h>
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uint32_t nb_ioapic_read(unsigned int index)
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{
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pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, index);
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return pci_read_config32(SOC_GNB_DEV, NB_IOAPIC_DATA);
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}
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void nb_ioapic_write(unsigned int index, uint32_t value)
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{
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pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, index);
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pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_DATA, value);
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}
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void *get_ap_entry_ptr(void)
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{
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return (void *)nb_ioapic_read(AP_SCRATCH_REG);
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}
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void set_ap_entry_ptr(void *entry)
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{
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nb_ioapic_write(AP_SCRATCH_REG, (uintptr_t)entry);
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}
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