cd2afc0df0
Instead of defining the same functions for reading/clearing boot-mode switches from EC in every mainboard, add a common infrastructure to enable common functions for handling boot-mode switches if GOOGLE_CHROMEEC is being used. Only boards that were not moved to this new infrastructure are those that do not use GOOGLE_CHROMEEC or which rely on some mainboard specific mechanism for reading boot-mode switches. BUG=None BRANCH=None TEST=abuild compiles all boards successfully with and without ChromeOS option. Change-Id: I267aadea9e616464563df04b51a668b877f0d578 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17449 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
75 lines
2.3 KiB
C
75 lines
2.3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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* Copyright (C) 2015 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <rules.h>
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#include <soc/gpio.h>
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#include <string.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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/* The WP status pin lives on MF_ISH_GPIO_4 */
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#define WP_STATUS_PAD_CFG0 0x4838
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#define WP_STATUS_PAD_CFG1 0x483C
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#if ENV_RAMSTAGE
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#include <boot/coreboot_tables.h>
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#define ACTIVE_LOW 0
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#define ACTIVE_HIGH 1
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void fill_lb_gpios(struct lb_gpios *gpios)
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{
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struct lb_gpio chromeos_gpios[] = {
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{-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"},
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{-1, ACTIVE_HIGH, vboot_recovery_mode_enabled(), "recovery"},
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{-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"},
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{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
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{-1, ACTIVE_HIGH, 0, "power"},
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{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
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};
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lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
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}
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#endif /* ENV_RAMSTAGE */
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int get_write_protect_state(void)
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{
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/*
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* The vboot loader queries this function in romstage. The GPIOs have
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* not been set up yet as that configuration is done in ramstage.
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* Configuring this GPIO as input so that there isn't any ambiguity
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* in the reading.
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*/
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#if ENV_ROMSTAGE
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write32((void *)(COMMUNITY_GPEAST_BASE + WP_STATUS_PAD_CFG0),
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(PAD_PULL_UP_20K | PAD_GPIO_ENABLE | PAD_CONFIG0_GPI_DEFAULT));
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write32((void *)(COMMUNITY_GPEAST_BASE + WP_STATUS_PAD_CFG1),
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PAD_CONFIG1_DEFAULT0);
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#endif
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/* WP is enabled when the pin is reading high. */
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return (read32((void *)(COMMUNITY_GPEAST_BASE + WP_STATUS_PAD_CFG0))
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& PAD_VAL_HIGH);
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}
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static const struct cros_gpio cros_gpios[] = {
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CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
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CROS_GPIO_WP_AH(0x10013, CROS_GPIO_DEVICE_NAME),
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};
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void mainboard_chromeos_acpi_generate(void)
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{
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chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
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}
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