faaafb4db1
Also move the fch_* functions in the header file in the order they get called. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9b6c6ad744b26f8488015c38a84d7e21c7d7687a Reviewed-on: https://review.coreboot.org/c/coreboot/+/50093 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
120 lines
2.7 KiB
C
120 lines
2.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <drivers/i2c/designware/dw_i2c.h>
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#include <soc/acpi.h>
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#include <soc/cpu.h>
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#include <soc/data_fabric.h>
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#include <soc/iomap.h>
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#include <soc/pci_devs.h>
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#include <soc/southbridge.h>
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#include "chip.h"
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#include <fsp/api.h>
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/* Supplied by i2c.c */
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extern struct device_operations picasso_i2c_mmio_ops;
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/* Supplied by uart.c */
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extern struct device_operations picasso_uart_mmio_ops;
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struct device_operations cpu_bus_ops = {
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.read_resources = noop_read_resources,
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.set_resources = noop_set_resources,
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.init = mp_cpu_bus_init,
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.acpi_fill_ssdt = generate_cpu_entries,
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};
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const char *soc_acpi_name(const struct device *dev)
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{
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if (dev->path.type == DEVICE_PATH_DOMAIN)
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return "PCI0";
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if (dev->path.type != DEVICE_PATH_PCI)
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return NULL;
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if (dev->bus->dev->path.type == DEVICE_PATH_DOMAIN) {
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switch (dev->path.pci.devfn) {
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case GNB_DEVFN:
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return "GNB";
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case IOMMU_DEVFN:
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return "IOMM";
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case LPC_DEVFN:
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return "LPCB";
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case SMBUS_DEVFN:
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return "SBUS";
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default:
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printk(BIOS_WARNING, "Unknown root PCI device: dev: %d, fn: %d\n",
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PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn));
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return NULL;
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}
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}
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printk(BIOS_WARNING, "Unknown PCI device: dev: %d, fn: %d\n",
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PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn));
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return NULL;
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};
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static struct device_operations pci_domain_ops = {
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.read_resources = pci_domain_read_resources,
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.set_resources = pci_domain_set_resources,
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.scan_bus = pci_domain_scan_bus,
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.acpi_name = soc_acpi_name,
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};
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static void set_mmio_dev_ops(struct device *dev)
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{
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switch (dev->path.mmio.addr) {
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case APU_I2C2_BASE:
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case APU_I2C3_BASE:
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case APU_I2C4_BASE:
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dev->ops = &picasso_i2c_mmio_ops;
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break;
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case APU_UART0_BASE:
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case APU_UART1_BASE:
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case APU_UART2_BASE:
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case APU_UART3_BASE:
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dev->ops = &picasso_uart_mmio_ops;
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break;
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}
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}
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static void enable_dev(struct device *dev)
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{
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/* Set the operations if it is a special bus type */
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switch (dev->path.type) {
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case DEVICE_PATH_DOMAIN:
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dev->ops = &pci_domain_ops;
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break;
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case DEVICE_PATH_CPU_CLUSTER:
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dev->ops = &cpu_bus_ops;
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break;
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case DEVICE_PATH_MMIO:
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set_mmio_dev_ops(dev);
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break;
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default:
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break;
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}
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}
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static void soc_init(void *chip_info)
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{
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default_dev_ops_root.write_acpi_tables = agesa_write_acpi_tables;
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fsp_silicon_init(acpi_is_wakeup_s3());
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data_fabric_set_mmio_np();
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fch_init(chip_info);
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}
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static void soc_final(void *chip_info)
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{
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fch_final(chip_info);
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}
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struct chip_operations soc_amd_picasso_ops = {
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CHIP_NAME("AMD Picasso SOC")
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.enable_dev = enable_dev,
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.init = soc_init,
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.final = soc_final
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};
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