96195eeb71
This patch aligns tegra132 to the new SoC header include scheme. Also alphabetized headers in affected files since we touch them anyway. BUG=None TEST=Tested with whole series. Compiled Rush_Ryu. Change-Id: I5cdf4008a65db84f15c937ef53aab5e4d3ef24c4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d5c5c63d7b6399d3eb8a211b15d47829fe93a591 Original-Change-Id: Ifafd4d42d4fb04a1c37e8a5f23877c2b550cf44c Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/224505 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9369 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
78 lines
2.4 KiB
C
78 lines
2.4 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2013 Google Inc.
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* Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/io.h>
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#include <assert.h>
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#include <console/console.h>
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#include <soc/addressmap.h>
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#include <soc/pmc.h>
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#include <soc/power.h>
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static struct tegra_pmc_regs * const pmc = (void *)TEGRA_PMC_BASE;
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static int partition_powered(int id)
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{
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return read32(&pmc->pwrgate_status) & (0x1 << id);
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}
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void power_ungate_partition(uint32_t id)
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{
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printk(BIOS_INFO, "Ungating power partition %d.\n", id);
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if (!partition_powered(id)) {
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uint32_t pwrgate_toggle = read32(&pmc->pwrgate_toggle);
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pwrgate_toggle &= ~(PMC_PWRGATE_TOGGLE_PARTID_MASK);
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pwrgate_toggle |= (id << PMC_PWRGATE_TOGGLE_PARTID_SHIFT);
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pwrgate_toggle |= PMC_PWRGATE_TOGGLE_START;
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write32(pwrgate_toggle, &pmc->pwrgate_toggle);
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/* Wait for the request to be accepted. */
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while (read32(&pmc->pwrgate_toggle) & PMC_PWRGATE_TOGGLE_START)
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;
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printk(BIOS_DEBUG, "Power gate toggle request accepted.\n");
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/* Wait for the partition to be powered. */
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while (!partition_powered(id))
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;
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}
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printk(BIOS_INFO, "Ungated power partition %d.\n", id);
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}
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uint8_t pmc_rst_status(void)
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{
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return read32(&pmc->rst_status) & PMC_RST_STATUS_SOURCE_MASK;
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}
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static const char *pmc_rst_status_str[PMC_RST_STATUS_NUM_SOURCES] = {
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[PMC_RST_STATUS_SOURCE_POR] = "POR",
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[PMC_RST_STATUS_SOURCE_WATCHDOG] = "Watchdog",
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[PMC_RST_STATUS_SOURCE_SENSOR] = "Sensor",
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[PMC_RST_STATUS_SOURCE_SW_MAIN] = "SW Main",
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[PMC_RST_STATUS_SOURCE_LP0] = "LP0",
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};
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void pmc_print_rst_status(void)
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{
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uint8_t rst_status = pmc_rst_status();
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assert(rst_status < PMC_RST_STATUS_NUM_SOURCES);
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printk(BIOS_INFO, "PMC Reset Status: %s\n",
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pmc_rst_status_str[rst_status]);
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}
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