fcbebb61c5
No board in the tree selects this and it looks like the implementation was done at chipset level while it should be part of PCI subsystem. When enabled, at least AMD K8 and f14, f15tn and f16kb fail build test. Feature of placing prefetchable PCI memory above 4GB may not work if there is any 32-bit only prefetchable PCI BARs in the system. Change-Id: I40ded2c7d6d05f461423721aa5d78a78f9f9ce1e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8705 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> |
||
---|---|---|
.. | ||
dram | ||
oprom | ||
azalia_device.c | ||
cardbus_device.c | ||
cpu_device.c | ||
device.c | ||
device_romstage.c | ||
device_util.c | ||
hypertransport.c | ||
Kconfig | ||
Makefile.inc | ||
pci_class.c | ||
pci_device.c | ||
pci_early.c | ||
pci_ops.c | ||
pci_rom.c | ||
pciexp_device.c | ||
pcix_device.c | ||
pnp_device.c | ||
root_device.c | ||
smbus_ops.c | ||
software_i2c.c |