31f6320afe
Now that SAR support in VPD is deprecated in coreboot, there is no need for a separate Kconfig `WIFI_SAR_CBFS` as the SAR table is only supported as a CBFS file. This change drops the config `WIFI_SAR_CBFS` from drivers/wifi/generic/Kconfig and its selection in mb/google/.../Kconfig. wifi_sar_defaults.hex is added to CBFS only if CONFIG_WIFI_SAR_CBFS_FILEPATH is not empty because current mainboards do not provide a default SAR file in coreboot. Thus, CONFIG_WIFI_SAR_CBFS_FILEPATH is updated to have a default value of "". BUG=b:173465272 Cq-Depend: chromium:2757781 Change-Id: I0bb8f6e2511596e4503fe4d8c34439228ceaa3c7 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
96 lines
1.9 KiB
Text
96 lines
1.9 KiB
Text
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config BOARD_GOOGLE_BASEBOARD_DRALLION
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def_bool n
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select BOARD_ROMSIZE_KB_32768
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select DRIVERS_GFX_GENERIC
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select DRIVERS_I2C_GENERIC
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select DRIVERS_I2C_HID
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select DRIVERS_INTEL_ISH
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select DRIVERS_SPI_ACPI
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select DRIVERS_USB_ACPI
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select EC_GOOGLE_WILCO
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select GOOGLE_SMBIOS_MAINBOARD_VERSION
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select INTEL_LPSS_UART_FOR_CONSOLE
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select MAINBOARD_HAS_CHROMEOS
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select MAINBOARD_HAS_I2C_TPM_CR50
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select MAINBOARD_HAS_TPM2
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select SMBIOS_SERIAL_FROM_VPD if VPD
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select SOC_INTEL_COMETLAKE_1
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select SOC_INTEL_COMMON_BLOCK_HDA_VERB
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select SOC_INTEL_COMMON_BLOCK_SMM_ESPI_DISABLE
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select SYSTEM_TYPE_LAPTOP
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select TPM2
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select MAINBOARD_USES_IFD_EC_REGION
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select HAVE_SPD_IN_CBFS
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if BOARD_GOOGLE_BASEBOARD_DRALLION
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config CHROMEOS
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select GBB_FLAG_FORCE_DEV_SWITCH_ON
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select GBB_FLAG_FORCE_DEV_BOOT_USB
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select GBB_FLAG_FORCE_DEV_BOOT_ALTFW
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select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
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config CHROMEOS_WIFI_SAR
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bool "Enable SAR options for Chrome OS build"
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depends on CHROMEOS
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select DSAR_ENABLE
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select GEO_SAR_ENABLE
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select SAR_ENABLE
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select USE_SAR
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config DIMM_MAX
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int
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default 2
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config DIMM_SPD_SIZE
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int
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default 512
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config DRIVER_TPM_I2C_BUS
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hex
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default 0x4
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config DRIVER_TPM_I2C_ADDR
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hex
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default 0x50
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config TPM_TIS_ACPI_INTERRUPT
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int
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default 82 # GPE0_DW2_18 (GPP_D18)
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config POWER_OFF_ON_CR50_UPDATE
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bool
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default n
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config MAINBOARD_DIR
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string
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default "google/drallion"
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config MAINBOARD_FAMILY
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string
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default "Google_Drallion" if BOARD_GOOGLE_DRALLION
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config MAINBOARD_PART_NUMBER
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string
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default "Drallion" if BOARD_GOOGLE_DRALLION
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config UART_FOR_CONSOLE
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int
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default 0 if BOARD_GOOGLE_DRALLION
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config VARIANT_DIR
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string
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default "drallion" if BOARD_GOOGLE_DRALLION
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config DEVICETREE
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string
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default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb"
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config VBOOT
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select HAS_RECOVERY_MRC_CACHE
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select VBOOT_LID_SWITCH
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endif # BOARD_GOOGLE_BASEBOARD_DRALLION
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