Felix Held fd2982ec8a soc/amd/cezanne/fch: implement and use fch_clk_output_48Mhz ... Make sure that the 48MHz clock output that is typically used as a clock source for an I2S audio codec or a Super I/O chip. TEST=On Guybrush before and after this patch the final state of MISC_CLK_CNTL0 is 0x1006044, so BP_X48M0_OUTPUT_EN is set in both cases. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I38be344a95ccf166c344b2bddcb388fea437a4df Reviewed-on: https://review.coreboot.org/c/coreboot/+/56528 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2021-08-30 19:46:17 +00:00
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cezanne	soc/amd/cezanne/fch: implement and use fch_clk_output_48Mhz	2021-08-30 19:46:17 +00:00
common	soc/amd/common: Show current SPI speeds and modes	2021-08-30 18:53:56 +00:00
picasso	soc/amd: Show SPI settings in bootblock	2021-08-30 18:54:16 +00:00
stoneyridge	soc/amd: Show SPI settings in bootblock	2021-08-30 18:54:16 +00:00
Kconfig	soc/amd: rename common Kconfig and use wildcard for SoC-specific Kconfig	2020-11-19 14:29:14 +00:00