fd440bb79e
With reset default of the clockgen on this board the SATA clock which needs to be 100MHz depends on FSB BSEL straps. This explains why SATA was originally tested to be working but fails with CPUs operating at different FSB. This change sets a bit in the clockgen configuration which fixes the SATA clock. TESTED on with a 1333MHz FSB CPU. Change-Id: Ic2b8ca91920f015ae3265871bc092023302fefdc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
50 lines
1.3 KiB
Text
50 lines
1.3 KiB
Text
#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
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# Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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if BOARD_ASROCK_G41C_GS_R2_0
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select ARCH_X86
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select CPU_INTEL_SOCKET_LGA775
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select NORTHBRIDGE_INTEL_X4X
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select SOUTHBRIDGE_INTEL_I82801GX
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select SUPERIO_NUVOTON_NCT6776
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select HAVE_ACPI_TABLES
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select BOARD_ROMSIZE_KB_1024
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select INTEL_EDID
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select MAINBOARD_HAS_NATIVE_VGA_INIT
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select PCIEXP_ASPM
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select PCIEXP_CLK_PM
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select PCIEXP_L1_SUB_STATE
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select HAVE_OPTION_TABLE
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select HAVE_CMOS_DEFAULT
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select HAVE_ACPI_RESUME
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select DRIVERS_I2C_CK505
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config MAINBOARD_DIR
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string
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default "asrock/g41c-gs"
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config MAINBOARD_PART_NUMBER
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string
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default "G41C-GS R2.0"
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config MAX_CPUS
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int
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default 4
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endif # BOARD_ASROCK_G41C_GS_R2_0
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