13f1c2af8b
1. x86_setup_mtrr take address bit.
2. generic ht, pcix, pcie beidge...
3. scan bus and reset_bus
4. ht read ctrl to decide if the ht chain
is ready
5. Intel e7520 and e7525 support
6. new ich5r support
7. intel sb 6300 support.
yhlu patch
1. split x86_setup_mtrrs to fixed and var
2. if (resource->flags & IORESOURCE_FIXED ) return; in device.c pick_largest_resource
3. in_conherent.c K8_SCAN_PCI_BUS
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
245 lines
4.9 KiB
Text
245 lines
4.9 KiB
Text
uses HAVE_MP_TABLE
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uses HAVE_PIRQ_TABLE
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uses USE_FALLBACK_IMAGE
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uses HAVE_FALLBACK_BOOT
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uses HAVE_HARD_RESET
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uses IRQ_SLOT_COUNT
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uses HAVE_OPTION_TABLE
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uses CONFIG_MAX_CPUS
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uses CONFIG_MAX_PHYSICAL_CPUS
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uses CONFIG_LOGICAL_CPUS
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uses CONFIG_IOAPIC
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uses CONFIG_SMP
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uses FALLBACK_SIZE
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uses ROM_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_IMAGE_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_SECTION_OFFSET
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uses CONFIG_ROM_STREAM
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uses CONFIG_ROM_STREAM_START
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uses PAYLOAD_SIZE
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uses _ROMBASE
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uses XIP_ROM_SIZE
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uses XIP_ROM_BASE
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uses STACK_SIZE
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uses HEAP_SIZE
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uses USE_OPTION_TABLE
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uses LB_CKS_RANGE_START
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uses LB_CKS_RANGE_END
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uses LB_CKS_LOC
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uses MAINBOARD
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uses MAINBOARD_PART_NUMBER
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uses MAINBOARD_VENDOR
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uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
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uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
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uses LINUXBIOS_EXTRA_VERSION
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uses _RAMBASE
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uses TTYS0_BAUD
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uses TTYS0_BASE
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uses TTYS0_LCS
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uses DEFAULT_CONSOLE_LOGLEVEL
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uses MAXIMUM_CONSOLE_LOGLEVEL
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uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
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uses CONFIG_CONSOLE_SERIAL8250
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uses HAVE_INIT_TIMER
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uses CONFIG_GDB_STUB
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uses CONFIG_GDB_STUB
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uses CROSS_COMPILE
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uses CC
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uses HOSTCC
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uses OBJCOPY
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uses CONFIG_CHIP_NAME
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uses CONFIG_CONSOLE_VGA
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uses CONFIG_PCI_ROM_RUN
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uses K8_E0_MEM_HOLE_SIZEK
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uses USE_DCACHE_RAM
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uses DCACHE_RAM_BASE
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uses DCACHE_RAM_SIZE
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uses CONFIG_USE_INIT
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###
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### Build options
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###
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##
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## ROM_SIZE is the size of boot ROM that this board will use.
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##
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default ROM_SIZE=524288
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##
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## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
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##
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default FALLBACK_SIZE=131072
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##
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## Build code for the fallback boot
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##
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default HAVE_FALLBACK_BOOT=1
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##
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## Build code to reset the motherboard from linuxBIOS
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##
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default HAVE_HARD_RESET=1
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##
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## Build code to export a programmable irq routing table
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##
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default HAVE_PIRQ_TABLE=1
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default IRQ_SLOT_COUNT=22
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##
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## Build code to export an x86 MP table
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## Useful for specifying IRQ routing values
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##
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default HAVE_MP_TABLE=1
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##
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## Build code to export a CMOS option table
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##
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default HAVE_OPTION_TABLE=1
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##
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## Move the default LinuxBIOS cmos range off of AMD RTC registers
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##
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default LB_CKS_RANGE_START=49
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default LB_CKS_RANGE_END=122
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default LB_CKS_LOC=123
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##
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## Build code for SMP support
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## Only worry about 2 micro processors
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##
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default CONFIG_SMP=1
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default CONFIG_MAX_CPUS=8
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default CONFIG_MAX_PHYSICAL_CPUS=4
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default CONFIG_LOGICAL_CPUS=1
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#CHIP_NAME ?
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default CONFIG_CHIP_NAME=1
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#1G memory hole
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default K8_E0_MEM_HOLE_SIZEK=0x100000
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#VGA Console
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default CONFIG_CONSOLE_VGA=1
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default CONFIG_PCI_ROM_RUN=1
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##
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## enable CACHE_AS_RAM specifics
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##
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default USE_DCACHE_RAM=1
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default DCACHE_RAM_BASE=0xcf000
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default DCACHE_RAM_SIZE=0x1000
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default CONFIG_USE_INIT=1
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##
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## Build code to setup a generic IOAPIC
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##
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default CONFIG_IOAPIC=1
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##
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## Clean up the motherboard id strings
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##
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default MAINBOARD_VENDOR="Tyan"
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default MAINBOARD_PART_NUMBER="s4882"
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default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
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default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x4882
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###
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### LinuxBIOS layout values
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###
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## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
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default ROM_IMAGE_SIZE = 65536
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##
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## Use a small 8K stack
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##
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default STACK_SIZE=0x2000
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##
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## Use a small 16K heap
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##
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default HEAP_SIZE=0x4000
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##
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## Only use the option table in a normal image
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##
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default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
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##
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## LinuxBIOS C code runs at this location in RAM
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##
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default _RAMBASE=0x00004000
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##
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## Load the payload from the ROM
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##
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default CONFIG_ROM_STREAM = 1
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###
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### Defaults of options that you may want to override in the target config file
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###
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##
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## The default compiler
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##
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default CC="$(CROSS_COMPILE)gcc -m32"
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default HOSTCC="gcc"
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##
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## Disable the gdb stub by default
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##
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default CONFIG_GDB_STUB=0
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##
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## The Serial Console
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##
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# To Enable the Serial Console
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default CONFIG_CONSOLE_SERIAL8250=1
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## Select the serial console baud rate
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default TTYS0_BAUD=115200
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#default TTYS0_BAUD=57600
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#default TTYS0_BAUD=38400
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#default TTYS0_BAUD=19200
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#default TTYS0_BAUD=9600
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#default TTYS0_BAUD=4800
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#default TTYS0_BAUD=2400
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#default TTYS0_BAUD=1200
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# Select the serial console base port
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default TTYS0_BASE=0x3f8
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# Select the serial protocol
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# This defaults to 8 data bits, 1 stop bit, and no parity
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default TTYS0_LCS=0x3
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##
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### Select the linuxBIOS loglevel
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##
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## EMERG 1 system is unusable
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## ALERT 2 action must be taken immediately
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## CRIT 3 critical conditions
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## ERR 4 error conditions
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## WARNING 5 warning conditions
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## NOTICE 6 normal but significant condition
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## INFO 7 informational
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## DEBUG 8 debug-level messages
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## SPEW 9 Way too many details
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## Request this level of debugging output
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default DEFAULT_CONSOLE_LOGLEVEL=8
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## At a maximum only compile in this level of debugging
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default MAXIMUM_CONSOLE_LOGLEVEL=8
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##
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## Select power on after power fail setting
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default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
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### End Options.lb
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end
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