No description
fe0dd6fc93
Add this function and make it return 0, as there is no physical dev switch (at least I think this is what we are supposed to do). This is needed for elog to work, which is needed so we can test RTC properly. BUG=chrome-os-partner:52220 BRANCH=none TEST=boot on gru with CONFIG_ELOG_DEBUG enabled and see elog messages: elog_init() SF: Detected W25Q64 with sector size 0x1000, total 0x800000 elog_find_flash() FMAP: area RW_ELOG found @ 5d8000 (32768 bytes) elog_scan_flash() elog_is_buffer_clear(base=0x000000000031d668 size=4096) ELOG: flash area invalid elog_flash_erase(address=0x000000000031d668 offset=0x005d8000 size=4096) SF: Successfully erased 4096 bytes @ 0x5d8000 elog_prepare_empty() elog_flash_write(address=0x000000000031d668 offset=0x005d8000 size=8) elog_scan_flash() elog_is_buffer_clear(base=0x000000000031d668 size=4096) elog_is_header_valid() elog_update_event_buffer_state() elog_is_buffer_clear(base=0x000000000031d670 size=4088) elog_is_area_valid() ELOG: FLASH @0x000000000031d668 [SPI 0x005d8000] ELOG: area is 4096 bytes, full threshold 3834, shrink size 1024 elog_add_event_raw(type=16) out: cmd=0x44: 03 b9 44 00 00 00 00 00 in-header: 03 3f 00 00 04 00 00 00 in-data: 6e 4c 00 00 elog_flash_write(address=0x000000000031d670 offset=0x005d8008 size=11) ELOG: Event(16) added with size 11 elog_add_event_raw(type=17) out: cmd=0x44: 03 b9 44 00 00 00 00 00 in-header: 03 3f 00 00 04 00 00 00 in-data: 6e 4c 00 00 elog_flash_write(address=0x000000000031d67b offset=0x005d8013 size=13) ELOG: Event(17) added with size 13 elog_add_event_raw(type=A0) out: cmd=0x44: 03 b9 44 00 00 00 00 00 in-header: 03 3f 00 00 04 00 00 00 in-data: 6e 4c 00 00 elog_flash_write(address=0x000000000031d688 offset=0x005d8020 size=9) ELOG: Event(A0) added with size 9 elog_add_boot_reason: Logged dev mode boot I can't actually see the timestamp, but the EC traffic is visible. Change-Id: I82bcf296dce4f4d146edf90b23bfae955fbe9e3a Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: ffc7a7e0e7b136144d2a0b2ed21a543eafee49fa Original-Change-Id: I1489c6b874cc49495635aec0bf303f7098455716 Original-Signed-off-by: Simon Glass <sjg@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/353821 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@google.com> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/15305 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> |
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3rdparty | ||
Documentation | ||
payloads | ||
src | ||
util | ||
.clang-format | ||
.gitignore | ||
.gitmodules | ||
.gitreview | ||
COPYING | ||
MAINTAINERS | ||
Makefile | ||
Makefile.inc | ||
README | ||
toolchain.inc |
------------------------------------------------------------------------------- coreboot README ------------------------------------------------------------------------------- coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload. With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required. coreboot was formerly known as LinuxBIOS. Payloads -------- After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot. See http://www.coreboot.org/Payloads for a list of supported payloads. Supported Hardware ------------------ coreboot supports a wide range of chipsets, devices, and mainboards. For details please consult: * http://www.coreboot.org/Supported_Motherboards * http://www.coreboot.org/Supported_Chipsets_and_Devices Build Requirements ------------------ * make * gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of "unusual" things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that's worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case). * iasl (for targets with ACPI support) Optional: * doxygen (for generating/viewing documentation) * gdb (for better debugging facilities on some targets) * ncurses (for 'make menuconfig' and 'make nconfig') * flex and bison (for regenerating parsers) Building coreboot ----------------- Please consult http://www.coreboot.org/Build_HOWTO for details. Testing coreboot Without Modifying Your Hardware ------------------------------------------------ If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU. Please see http://www.coreboot.org/QEMU for details. Website and Mailing List ------------------------ Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website: http://www.coreboot.org You can contact us directly on the coreboot mailing list: http://www.coreboot.org/Mailinglist Copyright and License --------------------- The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details. coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details. This makes the resulting coreboot images licensed under the GPL, version 2.