feed329a0c
This change adds the southbridge related code to support the update of the AMD Family14 cpus to the rec C0 level. Some of the changes reside in mainboard folders but they reference changed files in the southbridge folder so they are included herein. Change-Id: Ib7786f9f697eaf0bf8abd9140c4dd0c42927ec7e Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Signed-off-by: Kerry She <kerry.she@amd.com> Signed-off-by: Kerry She <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/135 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
148 lines
4 KiB
C
148 lines
4 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <arch/io.h>
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#include <boot/tables.h>
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#include <cpu/x86/msr.h>
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#include <cpu/amd/mtrr.h>
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#include <device/pci_def.h>
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#include "SBPLATFORM.h"
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#include "chip.h"
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uint64_t uma_memory_base, uma_memory_size;
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u8 is_dev3_present(void);
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void set_pcie_dereset(void);
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void set_pcie_reset(void);
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void enable_int_gfx(void);
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/* GPIO6. */
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void enable_int_gfx(void)
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{
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volatile u8 *gpio_reg;
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#ifdef UNUSED_CODE
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RWPMIO(SB_PMIOA_REGEA, AccWidthUint8, ~(BIT0), BIT0); /* Disable the PCIB */
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RWPMIO(SB_PMIOA_REGF6, AccWidthUint8, ~(BIT0), BIT0); /* Disable Gec */
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#endif
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/* make sure the Acpi MMIO(fed80000) is accessible */
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RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0);
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gpio_reg = (volatile u8 *)ACPI_MMIO_BASE + 0xD00; /* IoMux Register */
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*(gpio_reg + 0x6) = 0x1; /* Int_vga_en */
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*(gpio_reg + 170) = 0x1; /* gpio_gate */
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gpio_reg = (volatile u8 *)ACPI_MMIO_BASE + 0x100; /* GPIO Registers */
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*(gpio_reg + 0x6) = 0x8;
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*(gpio_reg + 170) = 0x0;
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}
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void set_pcie_dereset()
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{
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}
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void set_pcie_reset(void)
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{
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}
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u8 is_dev3_present(void)
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{
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return 0;
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}
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/*************************************************
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* enable the dedicated function in A785E-I board.
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* This function called early than rs780_enable.
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*************************************************/
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static void a785e_i_enable(device_t dev)
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{
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/* Leave it for furture use. */
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/* struct mainboard_config *mainboard =
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(struct mainboard_config *)dev->chip_info; */
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printk(BIOS_INFO, "Mainboard A785E-I Enable. dev=0x%p\n", dev);
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#if (CONFIG_GFXUMA == 1)
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msr_t msr, msr2;
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/* TOP_MEM: the top of DRAM below 4G */
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msr = rdmsr(TOP_MEM);
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printk
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(BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
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__func__, msr.lo, msr.hi);
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/* TOP_MEM2: the top of DRAM above 4G */
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msr2 = rdmsr(TOP_MEM2);
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printk
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(BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
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__func__, msr2.lo, msr2.hi);
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/* refer to UMA Size Consideration in 780 BDG. */
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switch (msr.lo) {
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case 0x10000000: /* 256M system memory */
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uma_memory_size = 0x4000000; /* 64M recommended UMA */
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break;
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case 0x20000000: /* 512M system memory */
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uma_memory_size = 0x8000000; /* 128M recommended UMA */
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break;
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default: /* 1GB and above system memory */
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uma_memory_size = 0x10000000; /* 256M recommended UMA */
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break;
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}
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uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */
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printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
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__func__, uma_memory_size, uma_memory_base);
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/* TODO: TOP_MEM2 */
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#else
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uma_memory_size = 0x8000000; /* 128M recommended UMA */
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uma_memory_base = 0x38000000; /* 1GB system memory supposed */
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#endif
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set_pcie_dereset();
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enable_int_gfx();
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}
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int add_mainboard_resources(struct lb_memory *mem)
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{
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/* UMA is removed from system memory in the northbridge code, but
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* in some circumstances we want the memory mentioned as reserved.
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*/
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#if (CONFIG_GFXUMA == 1)
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printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
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uma_memory_base, uma_memory_size);
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lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
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uma_memory_size);
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#endif
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return 0;
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}
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struct chip_operations mainboard_ops = {
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CHIP_NAME("ADVANSUS A785E-I Mainboard")
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.enable_dev = a785e_i_enable,
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};
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