coreboot-kgpe-d16/src/soc/rockchip/rk3399/timer.c
huang lin c14b54dd17 rockchip/rk3399: Add a stub implementation of the rk3399 SOC
Most things still need to be filled in, but this will allow
us to build boards which use this SOC.

BRANCH=none
BUG=chrome-os-partner:51537
TEST=with the rest of the patches applied Kevin board can be booted to
     Linux login propmt.

Change-Id: I6f2407ff578dcd3d0daed86dd03d8f5f4edcac53
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 27dfc39efe95025be2271e2e00e9df93b7907840
Original-Change-Id: I6f2407ff578dcd3d0daed86dd03d8f5f4edcac53
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/332385
Reviewed-on: https://review.coreboot.org/13915
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-13 23:37:55 +02:00

45 lines
1.2 KiB
C

/*
* This file is part of the coreboot project.
*
* Copyright 2016 Rockchip Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/io.h>
#include <delay.h>
#include <soc/timer.h>
#include <stdint.h>
#include <timer.h>
static uint64_t timer_raw_value(void)
{
uint64_t value0;
uint64_t value1;
value0 = (uint64_t)read32(&timer0_ptr->timer_cur_value0);
value1 = (uint64_t)read32(&timer0_ptr->timer_cur_value1);
return value0 | value1<<32;
}
void timer_monotonic_get(struct mono_time *mt)
{
mono_time_set_usecs(mt, timer_raw_value() / clocks_per_usec);
}
void init_timer(void)
{
write32(&timer0_ptr->timer_load_count0, TIMER_LOAD_VAL);
write32(&timer0_ptr->timer_load_count1, TIMER_LOAD_VAL);
write32(&timer0_ptr->timer_load_count2, 0);
write32(&timer0_ptr->timer_load_count3, 0);
write32(&timer0_ptr->timer_ctrl_reg, 1);
}