feed329a0c
This change adds the southbridge related code to support the update of the AMD Family14 cpus to the rec C0 level. Some of the changes reside in mainboard folders but they reference changed files in the southbridge folder so they are included herein. Change-Id: Ib7786f9f697eaf0bf8abd9140c4dd0c42927ec7e Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Signed-off-by: Kerry She <kerry.she@amd.com> Signed-off-by: Kerry She <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/135 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
36 lines
1.2 KiB
Makefile
Executable file
36 lines
1.2 KiB
Makefile
Executable file
#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2011 Advanced Micro Devices, Inc.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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#
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romstage-y += buildOpts.c
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romstage-y += agesawrapper.c
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romstage-y += dimmSpd.c
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romstage-y += BiosCallOuts.c
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romstage-y += PlatformGnbPcie.c
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ramstage-y += buildOpts.c
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ramstage-y += agesawrapper.c
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ramstage-y += dimmSpd.c
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ramstage-y += BiosCallOuts.c
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ramstage-y += PlatformGnbPcie.c
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ramstage-y += reset.c
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AGESA_ROOT ?= src/vendorcode/amd/agesa/f14
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subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += ../../../../$(AGESA_ROOT)
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#subdirs-$(CONFIG_AMD_SB_CIMX) += ../../../vendorcode/amd/cimx
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