coreboot-kgpe-d16/src/soc/amd/stoneyridge/monotonic_timer.c
Aaron Durbin 51e4c1a76c soc/amd/stoneyridge: remove dependence on TSC
The TSC rate is empirically swinging during early boot. That
leaves timestamps and udelay()s to not be correct. To rectify this
stop using TSC for all of these time sources. Instead use the
performance TSC which is at a fixed 100MHz clock. That provides
stable time sources and legit timestamps.

BUG=b:72378235,b:72170796

Change-Id: Ia2693c415c557aac687bcb48ee69358ea1c53d67
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-25 23:30:14 +00:00

38 lines
951 B
C

/*
* This file is part of the coreboot project.
*
* Copyright 2018 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <cpu/x86/msr.h>
#include <timer.h>
#include <timestamp.h>
#define CU_PTSC_MSR 0xc0010280
#define PTSC_FREQ_MHZ 100
void timer_monotonic_get(struct mono_time *mt)
{
mono_time_set_usecs(mt, timestamp_get());
}
uint64_t timestamp_get(void)
{
unsigned long long val;
msr_t msr;
msr = rdmsr(CU_PTSC_MSR);
val = ((unsigned long long)msr.hi << 32) | msr.lo;
return val / PTSC_FREQ_MHZ;
}