df60e8786c
Change-Id: Ic90dcff9d0b49a75a26556e4a1884a2954ef68f6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36063 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
47 lines
1.5 KiB
C
47 lines
1.5 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ops.h>
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#include <device/pci_def.h>
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#include <amdblocks/sata.h>
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#include <soc/southbridge.h>
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void soc_enable_sata_features(struct device *dev)
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{
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u8 *ahci_ptr;
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u32 misc_ctl, cap_cfg;
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u32 temp;
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/* unlock the write-protect */
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misc_ctl = pci_read_config32(dev, SATA_MISC_CONTROL_REG);
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misc_ctl |= SATA_MISC_SUBCLASS_WREN;
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pci_write_config32(dev, SATA_MISC_CONTROL_REG, misc_ctl);
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/* set the SATA AHCI mode to allow port expanders */
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ahci_ptr = (u8 *)(uintptr_t)ALIGN_DOWN(
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pci_read_config32(dev, PCI_BASE_ADDRESS_5), 256);
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cap_cfg = read32(ahci_ptr + SATA_CAPABILITIES_REG);
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cap_cfg |= SATA_CAPABILITY_SPM;
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write32(ahci_ptr + SATA_CAPABILITIES_REG, cap_cfg);
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/* lock the write-protect */
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temp = pci_read_config32(dev, SATA_MISC_CONTROL_REG);
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temp &= ~SATA_MISC_SUBCLASS_WREN;
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pci_write_config32(dev, SATA_MISC_CONTROL_REG, temp);
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};
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