c4fdb7b923
Change-Id: I9a4e57f8fd032f2824eab0e5b59d635710e3e24b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
39 lines
1.2 KiB
C
39 lines
1.2 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/*
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* Utilities for SMM setup
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*/
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#include <console/console.h>
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#include <cpu/x86/smm.h>
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#include <amdblocks/acpimmio.h>
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#include <soc/southbridge.h>
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#include <soc/smi.h>
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void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
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{
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printk(BIOS_DEBUG, "%s STUB!!!\n", __func__);
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}
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/** Set the EOS bit and enable SMI generation from southbridge */
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void enable_smi_generation(void)
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{
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uint32_t reg = smi_read32(SMI_REG_SMITRIG0);
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reg &= ~SMITRG0_SMIENB; /* Enable SMI generation */
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reg |= SMITRG0_EOS; /* Set EOS bit */
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smi_write32(SMI_REG_SMITRIG0, reg);
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}
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