112 lines
2.9 KiB
C
112 lines
2.9 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Google Inc
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#define __SIMPLE_DEVICE__
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#include <stdint.h>
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#include <stddef.h>
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#include <arch/io.h>
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#include <arch/early_variables.h>
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#include <boot/coreboot_tables.h>
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#include <console/uart.h>
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#include <device/pci.h>
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#include <device/pci_def.h>
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static unsigned int oxpcie_present CAR_GLOBAL;
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static ROMSTAGE_CONST u32 uart0_base = CONFIG_EARLY_PCI_MMIO_BASE + 0x1000;
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static ROMSTAGE_CONST u32 uart1_base = CONFIG_EARLY_PCI_MMIO_BASE + 0x2000;
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int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base)
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{
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pci_devfn_t device = PCI_DEV(bus, dev, 0);
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u32 id = pci_read_config32(device, PCI_VENDOR_ID);
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switch (id) {
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case 0xc1181415: /* e.g. Startech PEX1S1PMINI function 0 */
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/* On this device function 0 is the parallel port, and
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* function 3 is the serial port. So let's go look for
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* the UART.
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*/
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device = PCI_DEV(bus, dev, 3);
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id = pci_read_config32(device, PCI_VENDOR_ID);
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if (id != 0xc11b1415)
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return -1;
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break;
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case 0xc11b1415: /* e.g. Startech PEX1S1PMINI function 3 */
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case 0xc1581415: /* e.g. Startech MPEX2S952 */
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break;
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default:
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/* No UART here. */
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return -1;
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}
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/* Sanity-check, we assume fixed location. */
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if (mmio_base != CONFIG_EARLY_PCI_MMIO_BASE)
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return -1;
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/* Setup base address on device */
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pci_write_config32(device, PCI_BASE_ADDRESS_0, mmio_base);
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/* Enable memory on device */
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u16 reg16 = pci_read_config16(device, PCI_COMMAND);
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reg16 |= PCI_COMMAND_MEMORY;
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pci_write_config16(device, PCI_COMMAND, reg16);
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car_set_var(oxpcie_present, 1);
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return 0;
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}
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static int oxpcie_uart_active(void)
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{
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return (car_get_var(oxpcie_present));
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}
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unsigned int uart_platform_base(int idx)
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{
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if (idx == 0 && oxpcie_uart_active())
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return uart0_base;
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if (idx == 1 && oxpcie_uart_active())
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return uart1_base;
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return 0;
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}
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#ifndef __PRE_RAM__
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void oxford_remap(u32 new_base)
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{
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uart0_base = new_base + 0x1000;
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uart1_base = new_base + 0x2000;
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}
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void uart_fill_lb(void *data)
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{
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struct lb_serial serial;
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serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
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serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
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serial.baud = default_baudrate();
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lb_add_serial(&serial, data);
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lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
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}
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#endif
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unsigned int uart_platform_refclk(void)
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{
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return 62500000;
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}
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