coreboot-kgpe-d16/src
Kyösti Mälkki ff556ca995 cpu/x86/lapic: Split virtual_wire_mode_init()
Only the enable_lapic() part is required while doing
SMP init. Also disable_lapic() must not be called if
we rely on LAPIC for timer source.

Change-Id: Ib5e37c1a0a91fa4e9542141aa74f1c1876fee94e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-15 12:19:33 +00:00
..
acpi src/acpi to src/lib: Fix spelling errors 2021-10-05 18:06:39 +00:00
arch arch/x86/smbios: Add generation of type 20 table 2021-10-15 00:18:40 +00:00
commonlib src/acpi to src/lib: Fix spelling errors 2021-10-05 18:06:39 +00:00
console src/acpi to src/lib: Fix spelling errors 2021-10-05 18:06:39 +00:00
cpu cpu/x86/lapic: Split virtual_wire_mode_init() 2021-10-15 12:19:33 +00:00
device src/acpi to src/lib: Fix spelling errors 2021-10-05 18:06:39 +00:00
drivers drivers/pc80/tpm: Fix wrong debug message 2021-10-13 13:57:05 +00:00
ec ec/google/chromeec: Register USB-C mux operations 2021-10-06 22:20:32 +00:00
include arch/x86/smbios: Add generation of type 20 table 2021-10-15 00:18:40 +00:00
lib lib/thread: Remove thread stack alignment requirement 2021-10-05 22:40:25 +00:00
mainboard mainboard: Drop invalid `VGA_BIOS_FILE` defaults 2021-10-15 09:08:35 +00:00
northbridge nb/intel/haswell: Add HDAU ACPI device 2021-10-13 17:47:01 +00:00
security security/vboot: Remove vb2ex_hwcrypto stubs 2021-10-07 05:26:19 +00:00
soc soc/intel/alderlake: fix NULL pointer dereference 2021-10-15 00:15:07 +00:00
southbridge sb/intel/lynxpoint: Enable PCIe Clock PM and ASPM L1 2021-10-14 11:17:52 +00:00
superio src/soc to src/superio: Fix spelling errors 2021-10-05 18:07:08 +00:00
vendorcode vc/amd/fsp/cezanne: Add UPD fsp_owns_pcie_resets to FSP-M for Cezanne 2021-10-11 15:55:35 +00:00
Kconfig lib/thread: Switch to using CPU_INFO_V2 2021-10-05 22:39:16 +00:00