coreboot-kgpe-d16/src/soc
Martin Roth ffcd9393a4 soc/intel/fsp_baytrail: Adjust root port INT routing
Adjust the root port INT routing based on Bay Trail spec:
Document Number: 538136, Rev. 3.9

Table 241. Interrupt Generated for INT[A-D] Interrupts
             INTA  INTB  INTC  INTD
Root Port 1 INTA# INTB# INTC# INTD#
Root Port 2 INTD# INTA# INTB# INTC#
Root Port 3 INTC# INTD# INTA# INTB#
Root Port 4 INTB# INTC# INTD# INTA#

Change-Id: I22a8c0bc6ad731dfb79385d6e165f1ec0a07507d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12684
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Ben Gardner <gardner.ben@gmail.com>
2015-12-17 18:08:52 +01:00
..
broadcom/cygnus arm/arm64: Generalize bootblock C entry point 2015-11-11 05:08:07 +01:00
imgtec/pistachio tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00
intel soc/intel/fsp_baytrail: Adjust root port INT routing 2015-12-17 18:08:52 +01:00
marvell/bg4cd arm/arm64: Generalize bootblock C entry point 2015-11-11 05:08:07 +01:00
mediatek/mt8173 soc/mediatek/mt8173: SPI_ATOMIC_SEQUENCING depends on SPI_FLASH 2015-12-10 16:37:05 +01:00
nvidia arm64: tegra132: tegra210: Remove old arm64/stage_entry.S 2015-11-17 21:31:20 +01:00
qualcomm/ipq806x cbfs_spi: enable CBFS access in early romstage 2015-12-03 14:17:04 +01:00
rockchip/rk3288 google/veyron*: Pulse the i2c clock once if sda was low 2015-11-18 16:29:16 +01:00
samsung soc/samsung/exynos5250: Implement hard_reset() 2015-12-16 00:41:03 +01:00
ucb/riscv tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00