892 lines
18 KiB
C
892 lines
18 KiB
C
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/*
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* Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <limits.h>
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#include <libfdt.h>
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#include <platform_def.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/st/bsec.h>
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#include <lib/mmio.h>
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#include <lib/spinlock.h>
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#define BSEC_IP_VERSION_1_0 0x10
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#define BSEC_COMPAT "st,stm32mp15-bsec"
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#define OTP_ACCESS_SIZE (round_up(OTP_MAX_SIZE, __WORD_BIT) / __WORD_BIT)
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static uint32_t otp_nsec_access[OTP_ACCESS_SIZE] __unused;
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static uint32_t bsec_power_safmem(bool power);
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/* BSEC access protection */
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static spinlock_t bsec_spinlock;
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static uintptr_t bsec_base;
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static void bsec_lock(void)
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{
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if (stm32mp_lock_available()) {
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spin_lock(&bsec_spinlock);
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}
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}
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static void bsec_unlock(void)
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{
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if (stm32mp_lock_available()) {
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spin_unlock(&bsec_spinlock);
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}
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}
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static int bsec_get_dt_node(struct dt_node_info *info)
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{
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int node;
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node = dt_get_node(info, -1, BSEC_COMPAT);
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if (node < 0) {
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return -FDT_ERR_NOTFOUND;
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}
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return node;
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}
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#if defined(IMAGE_BL32)
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static void enable_non_secure_access(uint32_t otp)
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{
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otp_nsec_access[otp / __WORD_BIT] |= BIT(otp % __WORD_BIT);
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if (bsec_shadow_register(otp) != BSEC_OK) {
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panic();
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}
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}
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static bool non_secure_can_access(uint32_t otp)
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{
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return (otp_nsec_access[otp / __WORD_BIT] &
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BIT(otp % __WORD_BIT)) != 0;
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}
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static int bsec_dt_otp_nsec_access(void *fdt, int bsec_node)
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{
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int bsec_subnode;
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fdt_for_each_subnode(bsec_subnode, fdt, bsec_node) {
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const fdt32_t *cuint;
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uint32_t reg;
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uint32_t i;
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uint32_t size;
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uint8_t status;
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cuint = fdt_getprop(fdt, bsec_subnode, "reg", NULL);
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if (cuint == NULL) {
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panic();
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}
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reg = fdt32_to_cpu(*cuint) / sizeof(uint32_t);
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if (reg < STM32MP1_UPPER_OTP_START) {
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continue;
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}
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status = fdt_get_status(bsec_subnode);
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if ((status & DT_NON_SECURE) == 0U) {
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continue;
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}
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size = fdt32_to_cpu(*(cuint + 1)) / sizeof(uint32_t);
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if ((fdt32_to_cpu(*(cuint + 1)) % sizeof(uint32_t)) != 0) {
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size++;
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}
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for (i = reg; i < (reg + size); i++) {
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enable_non_secure_access(i);
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}
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}
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return 0;
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}
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#endif
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static uint32_t otp_bank_offset(uint32_t otp)
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{
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assert(otp <= STM32MP1_OTP_MAX_ID);
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return ((otp & ~BSEC_OTP_MASK) >> BSEC_OTP_BANK_SHIFT) *
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sizeof(uint32_t);
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}
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static uint32_t bsec_check_error(uint32_t otp)
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{
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uint32_t bit = BIT(otp & BSEC_OTP_MASK);
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uint32_t bank = otp_bank_offset(otp);
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if ((mmio_read_32(bsec_base + BSEC_DISTURBED_OFF + bank) & bit) != 0U) {
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return BSEC_DISTURBED;
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}
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if ((mmio_read_32(bsec_base + BSEC_ERROR_OFF + bank) & bit) != 0U) {
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return BSEC_ERROR;
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}
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return BSEC_OK;
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}
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/*
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* bsec_probe: initialize BSEC driver.
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* return value: BSEC_OK if no error.
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*/
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uint32_t bsec_probe(void)
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{
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void *fdt;
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int node;
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struct dt_node_info bsec_info;
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if (fdt_get_address(&fdt) == 0) {
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panic();
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}
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node = bsec_get_dt_node(&bsec_info);
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if (node < 0) {
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panic();
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}
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bsec_base = bsec_info.base;
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#if defined(IMAGE_BL32)
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bsec_dt_otp_nsec_access(fdt, node);
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#endif
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return BSEC_OK;
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}
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/*
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* bsec_get_base: return BSEC base address.
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*/
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uint32_t bsec_get_base(void)
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{
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return bsec_base;
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}
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/*
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* bsec_set_config: enable and configure BSEC.
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* cfg: pointer to param structure used to set register.
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* return value: BSEC_OK if no error.
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*/
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uint32_t bsec_set_config(struct bsec_config *cfg)
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{
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uint32_t value;
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int32_t result;
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value = ((((uint32_t)cfg->freq << BSEC_CONF_FRQ_SHIFT) &
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BSEC_CONF_FRQ_MASK) |
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(((uint32_t)cfg->pulse_width << BSEC_CONF_PRG_WIDTH_SHIFT) &
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BSEC_CONF_PRG_WIDTH_MASK) |
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(((uint32_t)cfg->tread << BSEC_CONF_TREAD_SHIFT) &
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BSEC_CONF_TREAD_MASK));
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bsec_lock();
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mmio_write_32(bsec_base + BSEC_OTP_CONF_OFF, value);
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bsec_unlock();
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result = bsec_power_safmem((bool)cfg->power &
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BSEC_CONF_POWER_UP_MASK);
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if (result != BSEC_OK) {
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return result;
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}
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value = ((((uint32_t)cfg->upper_otp_lock << UPPER_OTP_LOCK_SHIFT) &
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UPPER_OTP_LOCK_MASK) |
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(((uint32_t)cfg->den_lock << DENREG_LOCK_SHIFT) &
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DENREG_LOCK_MASK) |
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(((uint32_t)cfg->prog_lock << GPLOCK_LOCK_SHIFT) &
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GPLOCK_LOCK_MASK));
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bsec_lock();
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mmio_write_32(bsec_base + BSEC_OTP_LOCK_OFF, value);
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bsec_unlock();
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return BSEC_OK;
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}
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/*
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* bsec_get_config: return config parameters set in BSEC registers.
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* cfg: config param return.
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* return value: BSEC_OK if no error.
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*/
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uint32_t bsec_get_config(struct bsec_config *cfg)
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{
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uint32_t value;
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if (cfg == NULL) {
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return BSEC_INVALID_PARAM;
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}
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value = mmio_read_32(bsec_base + BSEC_OTP_CONF_OFF);
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cfg->power = (uint8_t)((value & BSEC_CONF_POWER_UP_MASK) >>
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BSEC_CONF_POWER_UP_SHIFT);
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cfg->freq = (uint8_t)((value & BSEC_CONF_FRQ_MASK) >>
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BSEC_CONF_FRQ_SHIFT);
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cfg->pulse_width = (uint8_t)((value & BSEC_CONF_PRG_WIDTH_MASK) >>
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BSEC_CONF_PRG_WIDTH_SHIFT);
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cfg->tread = (uint8_t)((value & BSEC_CONF_TREAD_MASK) >>
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BSEC_CONF_TREAD_SHIFT);
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value = mmio_read_32(bsec_base + BSEC_OTP_LOCK_OFF);
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cfg->upper_otp_lock = (uint8_t)((value & UPPER_OTP_LOCK_MASK) >>
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UPPER_OTP_LOCK_SHIFT);
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cfg->den_lock = (uint8_t)((value & DENREG_LOCK_MASK) >>
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DENREG_LOCK_SHIFT);
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cfg->prog_lock = (uint8_t)((value & GPLOCK_LOCK_MASK) >>
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GPLOCK_LOCK_SHIFT);
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return BSEC_OK;
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}
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/*
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* bsec_shadow_register: copy SAFMEM OTP to BSEC data.
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* otp: OTP number.
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* return value: BSEC_OK if no error.
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*/
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uint32_t bsec_shadow_register(uint32_t otp)
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{
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uint32_t result;
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bool power_up = false;
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if (otp > STM32MP1_OTP_MAX_ID) {
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return BSEC_INVALID_PARAM;
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}
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/* Check if shadowing of OTP is locked */
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if (bsec_read_sr_lock(otp)) {
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VERBOSE("BSEC: OTP %i is locked and will not be refreshed\n",
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otp);
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}
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if ((bsec_get_status() & BSEC_MODE_PWR_MASK) == 0U) {
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result = bsec_power_safmem(true);
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if (result != BSEC_OK) {
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return result;
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}
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power_up = true;
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}
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bsec_lock();
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/* Set BSEC_OTP_CTRL_OFF and set ADDR with the OTP value */
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mmio_write_32(bsec_base + BSEC_OTP_CTRL_OFF, otp | BSEC_READ);
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while ((bsec_get_status() & BSEC_MODE_BUSY_MASK) != 0U) {
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;
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}
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result = bsec_check_error(otp);
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bsec_unlock();
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if (power_up) {
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if (bsec_power_safmem(false) != BSEC_OK) {
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panic();
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}
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}
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return result;
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}
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/*
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* bsec_read_otp: read an OTP data value.
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* val: read value.
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* otp: OTP number.
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* return value: BSEC_OK if no error.
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*/
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uint32_t bsec_read_otp(uint32_t *val, uint32_t otp)
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{
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uint32_t result;
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if (otp > STM32MP1_OTP_MAX_ID) {
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return BSEC_INVALID_PARAM;
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}
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bsec_lock();
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*val = mmio_read_32(bsec_base + BSEC_OTP_DATA_OFF +
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(otp * sizeof(uint32_t)));
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result = bsec_check_error(otp);
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bsec_unlock();
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return result;
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}
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/*
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* bsec_write_otp: write value in BSEC data register.
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* val: value to write.
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* otp: OTP number.
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* return value: BSEC_OK if no error.
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*/
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uint32_t bsec_write_otp(uint32_t val, uint32_t otp)
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{
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uint32_t result;
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if (otp > STM32MP1_OTP_MAX_ID) {
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return BSEC_INVALID_PARAM;
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}
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/* Check if programming of OTP is locked */
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if (bsec_read_sw_lock(otp)) {
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VERBOSE("BSEC: OTP %i is locked and write will be ignored\n",
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otp);
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}
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bsec_lock();
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mmio_write_32(bsec_base + BSEC_OTP_DATA_OFF +
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(otp * sizeof(uint32_t)), val);
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result = bsec_check_error(otp);
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bsec_unlock();
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return result;
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}
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/*
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* bsec_program_otp: program a bit in SAFMEM after the prog.
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* The OTP data is not refreshed.
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* val: value to program.
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* otp: OTP number.
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* return value: BSEC_OK if no error.
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*/
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uint32_t bsec_program_otp(uint32_t val, uint32_t otp)
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{
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uint32_t result;
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bool power_up = false;
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if (otp > STM32MP1_OTP_MAX_ID) {
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return BSEC_INVALID_PARAM;
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}
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/* Check if programming of OTP is locked */
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if (bsec_read_sp_lock(otp)) {
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WARN("BSEC: OTP locked, prog will be ignored\n");
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}
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if ((mmio_read_32(bsec_base + BSEC_OTP_LOCK_OFF) &
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BIT(BSEC_LOCK_PROGRAM)) != 0U) {
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|
|
WARN("BSEC: GPLOCK activated, prog will be ignored\n");
|
||
|
|
}
|
||
|
|
|
||
|
|
if ((bsec_get_status() & BSEC_MODE_PWR_MASK) == 0U) {
|
||
|
|
result = bsec_power_safmem(true);
|
||
|
|
|
||
|
|
if (result != BSEC_OK) {
|
||
|
|
return result;
|
||
|
|
}
|
||
|
|
|
||
|
|
power_up = true;
|
||
|
|
}
|
||
|
|
|
||
|
|
bsec_lock();
|
||
|
|
|
||
|
|
/* Set value in write register */
|
||
|
|
mmio_write_32(bsec_base + BSEC_OTP_WRDATA_OFF, val);
|
||
|
|
|
||
|
|
/* Set BSEC_OTP_CTRL_OFF and set ADDR with the OTP value */
|
||
|
|
mmio_write_32(bsec_base + BSEC_OTP_CTRL_OFF, otp | BSEC_WRITE);
|
||
|
|
|
||
|
|
while ((bsec_get_status() & BSEC_MODE_BUSY_MASK) != 0U) {
|
||
|
|
;
|
||
|
|
}
|
||
|
|
|
||
|
|
if ((bsec_get_status() & BSEC_MODE_PROGFAIL_MASK) != 0U) {
|
||
|
|
result = BSEC_PROG_FAIL;
|
||
|
|
} else {
|
||
|
|
result = bsec_check_error(otp);
|
||
|
|
}
|
||
|
|
|
||
|
|
bsec_unlock();
|
||
|
|
|
||
|
|
if (power_up) {
|
||
|
|
if (bsec_power_safmem(false) != BSEC_OK) {
|
||
|
|
panic();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return result;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* bsec_permanent_lock_otp: permanent lock of OTP in SAFMEM.
|
||
|
|
* otp: OTP number.
|
||
|
|
* return value: BSEC_OK if no error.
|
||
|
|
*/
|
||
|
|
uint32_t bsec_permanent_lock_otp(uint32_t otp)
|
||
|
|
{
|
||
|
|
uint32_t result;
|
||
|
|
bool power_up = false;
|
||
|
|
uint32_t data;
|
||
|
|
uint32_t addr;
|
||
|
|
|
||
|
|
if (otp > STM32MP1_OTP_MAX_ID) {
|
||
|
|
return BSEC_INVALID_PARAM;
|
||
|
|
}
|
||
|
|
|
||
|
|
if ((bsec_get_status() & BSEC_MODE_PWR_MASK) == 0U) {
|
||
|
|
result = bsec_power_safmem(true);
|
||
|
|
|
||
|
|
if (result != BSEC_OK) {
|
||
|
|
return result;
|
||
|
|
}
|
||
|
|
|
||
|
|
power_up = true;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (otp < STM32MP1_UPPER_OTP_START) {
|
||
|
|
addr = otp >> ADDR_LOWER_OTP_PERLOCK_SHIFT;
|
||
|
|
data = DATA_LOWER_OTP_PERLOCK_BIT <<
|
||
|
|
((otp & DATA_LOWER_OTP_PERLOCK_MASK) << 1U);
|
||
|
|
} else {
|
||
|
|
addr = (otp >> ADDR_UPPER_OTP_PERLOCK_SHIFT) + 2U;
|
||
|
|
data = DATA_UPPER_OTP_PERLOCK_BIT <<
|
||
|
|
(otp & DATA_UPPER_OTP_PERLOCK_MASK);
|
||
|
|
}
|
||
|
|
|
||
|
|
bsec_lock();
|
||
|
|
|
||
|
|
/* Set value in write register */
|
||
|
|
mmio_write_32(bsec_base + BSEC_OTP_WRDATA_OFF, data);
|
||
|
|
|
||
|
|
/* Set BSEC_OTP_CTRL_OFF and set ADDR with the OTP value */
|
||
|
|
mmio_write_32(bsec_base + BSEC_OTP_CTRL_OFF,
|
||
|
|
addr | BSEC_WRITE | BSEC_LOCK);
|
||
|
|
|
||
|
|
while ((bsec_get_status() & BSEC_MODE_BUSY_MASK) != 0U) {
|
||
|
|
;
|
||
|
|
}
|
||
|
|
|
||
|
|
if ((bsec_get_status() & BSEC_MODE_PROGFAIL_MASK) != 0U) {
|
||
|
|
result = BSEC_PROG_FAIL;
|
||
|
|
} else {
|
||
|
|
result = bsec_check_error(otp);
|
||
|
|
}
|
||
|
|
|
||
|
|
bsec_unlock();
|
||
|
|
|
||
|
|
if (power_up) {
|
||
|
|
if (bsec_power_safmem(false) != BSEC_OK) {
|
||
|
|
panic();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return result;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* bsec_write_debug_conf: write value in debug feature
|
||
|
|
* to enable/disable debug service.
|
||
|
|
* val: value to write.
|
||
|
|
* return value: BSEC_OK if no error.
|
||
|
|
*/
|
||
|
|
uint32_t bsec_write_debug_conf(uint32_t val)
|
||
|
|
{
|
||
|
|
uint32_t result = BSEC_ERROR;
|
||
|
|
uint32_t masked_val = val & BSEC_DEN_ALL_MSK;
|
||
|
|
|
||
|
|
bsec_lock();
|
||
|
|
|
||
|
|
mmio_write_32(bsec_base + BSEC_DEN_OFF, masked_val);
|
||
|
|
|
||
|
|
if ((mmio_read_32(bsec_base + BSEC_DEN_OFF) ^ masked_val) == 0U) {
|
||
|
|
result = BSEC_OK;
|
||
|
|
}
|
||
|
|
|
||
|
|
bsec_unlock();
|
||
|
|
|
||
|
|
return result;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* bsec_read_debug_conf: read debug configuration.
|
||
|
|
*/
|
||
|
|
uint32_t bsec_read_debug_conf(void)
|
||
|
|
{
|
||
|
|
return mmio_read_32(bsec_base + BSEC_DEN_OFF);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* bsec_get_status: return status register value.
|
||
|
|
*/
|
||
|
|
uint32_t bsec_get_status(void)
|
||
|
|
{
|
||
|
|
return mmio_read_32(bsec_base + BSEC_OTP_STATUS_OFF);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* bsec_get_hw_conf: return hardware configuration.
|
||
|
|
*/
|
||
|
|
uint32_t bsec_get_hw_conf(void)
|
||
|
|
{
|
||
|
|
return mmio_read_32(bsec_base + BSEC_IPHW_CFG_OFF);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* bsec_get_version: return BSEC version.
|
||
|
|
*/
|
||
|
|
uint32_t bsec_get_version(void)
|
||
|
|
{
|
||
|
|
return mmio_read_32(bsec_base + BSEC_IPVR_OFF);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* bsec_get_id: return BSEC ID.
|
||
|
|
*/
|
||
|
|
uint32_t bsec_get_id(void)
|
||
|
|
{
|
||
|
|
return mmio_read_32(bsec_base + BSEC_IP_ID_OFF);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* bsec_get_magic_id: return BSEC magic number.
|
||
|
|
*/
|
||
|
|
uint32_t bsec_get_magic_id(void)
|
||
|
|
{
|
||
|
|
return mmio_read_32(bsec_base + BSEC_IP_MAGIC_ID_OFF);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* bsec_write_sr_lock: write shadow-read lock.
|
||
|
|
* otp: OTP number.
|
||
|
|
* value: value to write in the register.
|
||
|
|
* Must be always 1.
|
||
|
|
* return: true if OTP is locked, else false.
|
||
|
|
*/
|
||
|
|
bool bsec_write_sr_lock(uint32_t otp, uint32_t value)
|
||
|
|
{
|
||
|
|
bool result = false;
|
||
|
|
uint32_t bank = otp_bank_offset(otp);
|
||
|
|
uint32_t bank_value;
|
||
|
|
uint32_t otp_mask = BIT(otp & BSEC_OTP_MASK);
|
||
|
|
|
||
|
|
bsec_lock();
|
||
|
|
|
||
|
|
bank_value = mmio_read_32(bsec_base + BSEC_SRLOCK_OFF + bank);
|
||
|
|
|
||
|
|
if ((bank_value & otp_mask) == value) {
|
||
|
|
/*
|
||
|
|
* In case of write don't need to write,
|
||
|
|
* the lock is already set.
|
||
|
|
*/
|
||
|
|
if (value != 0U) {
|
||
|
|
result = true;
|
||
|
|
}
|
||
|
|
} else {
|
||
|
|
if (value != 0U) {
|
||
|
|
bank_value = bank_value | otp_mask;
|
||
|
|
} else {
|
||
|
|
bank_value = bank_value & ~otp_mask;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* We can write 0 in all other OTP
|
||
|
|
* if the lock is activated in one of other OTP.
|
||
|
|
* Write 0 has no effect.
|
||
|
|
*/
|
||
|
|
mmio_write_32(bsec_base + BSEC_SRLOCK_OFF + bank, bank_value);
|
||
|
|
result = true;
|
||
|
|
}
|
||
|
|
|
||
|
|
bsec_unlock();
|
||
|
|
|
||
|
|
return result;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* bsec_read_sr_lock: read shadow-read lock.
|
||
|
|
* otp: OTP number.
|
||
|
|
* return: true if otp is locked, else false.
|
||
|
|
*/
|
||
|
|
bool bsec_read_sr_lock(uint32_t otp)
|
||
|
|
{
|
||
|
|
uint32_t bank = otp_bank_offset(otp);
|
||
|
|
uint32_t otp_mask = BIT(otp & BSEC_OTP_MASK);
|
||
|
|
uint32_t bank_value = mmio_read_32(bsec_base + BSEC_SRLOCK_OFF + bank);
|
||
|
|
|
||
|
|
return (bank_value & otp_mask) != 0U;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* bsec_write_sw_lock: write shadow-write lock.
|
||
|
|
* otp: OTP number.
|
||
|
|
* value: Value to write in the register.
|
||
|
|
* Must be always 1.
|
||
|
|
* return: true if OTP is locked, else false.
|
||
|
|
*/
|
||
|
|
bool bsec_write_sw_lock(uint32_t otp, uint32_t value)
|
||
|
|
{
|
||
|
|
bool result = false;
|
||
|
|
uint32_t bank = otp_bank_offset(otp);
|
||
|
|
uint32_t otp_mask = BIT(otp & BSEC_OTP_MASK);
|
||
|
|
uint32_t bank_value;
|
||
|
|
|
||
|
|
bsec_lock();
|
||
|
|
|
||
|
|
bank_value = mmio_read_32(bsec_base + BSEC_SWLOCK_OFF + bank);
|
||
|
|
|
||
|
|
if ((bank_value & otp_mask) == value) {
|
||
|
|
/*
|
||
|
|
* In case of write don't need to write,
|
||
|
|
* the lock is already set.
|
||
|
|
*/
|
||
|
|
if (value != 0U) {
|
||
|
|
result = true;
|
||
|
|
}
|
||
|
|
} else {
|
||
|
|
if (value != 0U) {
|
||
|
|
bank_value = bank_value | otp_mask;
|
||
|
|
} else {
|
||
|
|
bank_value = bank_value & ~otp_mask;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* We can write 0 in all other OTP
|
||
|
|
* if the lock is activated in one of other OTP.
|
||
|
|
* Write 0 has no effect.
|
||
|
|
*/
|
||
|
|
mmio_write_32(bsec_base + BSEC_SWLOCK_OFF + bank, bank_value);
|
||
|
|
result = true;
|
||
|
|
}
|
||
|
|
|
||
|
|
bsec_unlock();
|
||
|
|
|
||
|
|
return result;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* bsec_read_sw_lock: read shadow-write lock.
|
||
|
|
* otp: OTP number.
|
||
|
|
* return: true if OTP is locked, else false.
|
||
|
|
*/
|
||
|
|
bool bsec_read_sw_lock(uint32_t otp)
|
||
|
|
{
|
||
|
|
uint32_t bank = otp_bank_offset(otp);
|
||
|
|
uint32_t otp_mask = BIT(otp & BSEC_OTP_MASK);
|
||
|
|
uint32_t bank_value = mmio_read_32(bsec_base + BSEC_SWLOCK_OFF + bank);
|
||
|
|
|
||
|
|
return (bank_value & otp_mask) != 0U;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* bsec_write_sp_lock: write shadow-program lock.
|
||
|
|
* otp: OTP number.
|
||
|
|
* value: Value to write in the register.
|
||
|
|
* Must be always 1.
|
||
|
|
* return: true if OTP is locked, else false.
|
||
|
|
*/
|
||
|
|
bool bsec_write_sp_lock(uint32_t otp, uint32_t value)
|
||
|
|
{
|
||
|
|
bool result = false;
|
||
|
|
uint32_t bank = otp_bank_offset(otp);
|
||
|
|
uint32_t bank_value;
|
||
|
|
uint32_t otp_mask = BIT(otp & BSEC_OTP_MASK);
|
||
|
|
|
||
|
|
bsec_lock();
|
||
|
|
|
||
|
|
bank_value = mmio_read_32(bsec_base + BSEC_SPLOCK_OFF + bank);
|
||
|
|
|
||
|
|
if ((bank_value & otp_mask) == value) {
|
||
|
|
/*
|
||
|
|
* In case of write don't need to write,
|
||
|
|
* the lock is already set.
|
||
|
|
*/
|
||
|
|
if (value != 0U) {
|
||
|
|
result = true;
|
||
|
|
}
|
||
|
|
} else {
|
||
|
|
if (value != 0U) {
|
||
|
|
bank_value = bank_value | otp_mask;
|
||
|
|
} else {
|
||
|
|
bank_value = bank_value & ~otp_mask;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* We can write 0 in all other OTP
|
||
|
|
* if the lock is activated in one of other OTP.
|
||
|
|
* Write 0 has no effect.
|
||
|
|
*/
|
||
|
|
mmio_write_32(bsec_base + BSEC_SPLOCK_OFF + bank, bank_value);
|
||
|
|
result = true;
|
||
|
|
}
|
||
|
|
|
||
|
|
bsec_unlock();
|
||
|
|
|
||
|
|
return result;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* bsec_read_sp_lock: read shadow-program lock.
|
||
|
|
* otp: OTP number.
|
||
|
|
* return: true if OTP is locked, else false.
|
||
|
|
*/
|
||
|
|
bool bsec_read_sp_lock(uint32_t otp)
|
||
|
|
{
|
||
|
|
uint32_t bank = otp_bank_offset(otp);
|
||
|
|
uint32_t otp_mask = BIT(otp & BSEC_OTP_MASK);
|
||
|
|
uint32_t bank_value = mmio_read_32(bsec_base + BSEC_SPLOCK_OFF + bank);
|
||
|
|
|
||
|
|
return (bank_value & otp_mask) != 0U;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* bsec_wr_lock: Read permanent lock status.
|
||
|
|
* otp: OTP number.
|
||
|
|
* return: true if OTP is locked, else false.
|
||
|
|
*/
|
||
|
|
bool bsec_wr_lock(uint32_t otp)
|
||
|
|
{
|
||
|
|
uint32_t bank = otp_bank_offset(otp);
|
||
|
|
uint32_t lock_bit = BIT(otp & BSEC_OTP_MASK);
|
||
|
|
|
||
|
|
if ((mmio_read_32(bsec_base + BSEC_WRLOCK_OFF + bank) &
|
||
|
|
lock_bit) != 0U) {
|
||
|
|
/*
|
||
|
|
* In case of write don't need to write,
|
||
|
|
* the lock is already set.
|
||
|
|
*/
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* bsec_otp_lock: Lock Upper OTP or Global programming or debug enable
|
||
|
|
* service: Service to lock see header file.
|
||
|
|
* value: Value to write must always set to 1 (only use for debug purpose).
|
||
|
|
* return: BSEC_OK if succeed.
|
||
|
|
*/
|
||
|
|
uint32_t bsec_otp_lock(uint32_t service, uint32_t value)
|
||
|
|
{
|
||
|
|
uintptr_t reg = bsec_base + BSEC_OTP_LOCK_OFF;
|
||
|
|
|
||
|
|
switch (service) {
|
||
|
|
case BSEC_LOCK_UPPER_OTP:
|
||
|
|
mmio_write_32(reg, value << BSEC_LOCK_UPPER_OTP);
|
||
|
|
break;
|
||
|
|
case BSEC_LOCK_DEBUG:
|
||
|
|
mmio_write_32(reg, value << BSEC_LOCK_DEBUG);
|
||
|
|
break;
|
||
|
|
case BSEC_LOCK_PROGRAM:
|
||
|
|
mmio_write_32(reg, value << BSEC_LOCK_PROGRAM);
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
return BSEC_INVALID_PARAM;
|
||
|
|
}
|
||
|
|
|
||
|
|
return BSEC_OK;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* bsec_power_safmem: Activate or deactivate SAFMEM power.
|
||
|
|
* power: true to power up, false to power down.
|
||
|
|
* return: BSEC_OK if succeed.
|
||
|
|
*/
|
||
|
|
static uint32_t bsec_power_safmem(bool power)
|
||
|
|
{
|
||
|
|
uint32_t register_val;
|
||
|
|
uint32_t timeout = BSEC_TIMEOUT_VALUE;
|
||
|
|
|
||
|
|
bsec_lock();
|
||
|
|
|
||
|
|
register_val = mmio_read_32(bsec_base + BSEC_OTP_CONF_OFF);
|
||
|
|
|
||
|
|
if (power) {
|
||
|
|
register_val |= BSEC_CONF_POWER_UP_MASK;
|
||
|
|
} else {
|
||
|
|
register_val &= ~BSEC_CONF_POWER_UP_MASK;
|
||
|
|
}
|
||
|
|
|
||
|
|
mmio_write_32(bsec_base + BSEC_OTP_CONF_OFF, register_val);
|
||
|
|
|
||
|
|
/* Waiting loop */
|
||
|
|
if (power) {
|
||
|
|
while (((bsec_get_status() & BSEC_MODE_PWR_MASK) == 0U) &&
|
||
|
|
(timeout != 0U)) {
|
||
|
|
timeout--;
|
||
|
|
}
|
||
|
|
} else {
|
||
|
|
while (((bsec_get_status() & BSEC_MODE_PWR_MASK) != 0U) &&
|
||
|
|
(timeout != 0U)) {
|
||
|
|
timeout--;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
bsec_unlock();
|
||
|
|
|
||
|
|
if (timeout == 0U) {
|
||
|
|
return BSEC_TIMEOUT;
|
||
|
|
}
|
||
|
|
|
||
|
|
return BSEC_OK;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* bsec_shadow_read_otp: Load OTP from SAFMEM and provide its value
|
||
|
|
* otp_value: read value.
|
||
|
|
* word: OTP number.
|
||
|
|
* return value: BSEC_OK if no error.
|
||
|
|
*/
|
||
|
|
uint32_t bsec_shadow_read_otp(uint32_t *otp_value, uint32_t word)
|
||
|
|
{
|
||
|
|
uint32_t result;
|
||
|
|
|
||
|
|
result = bsec_shadow_register(word);
|
||
|
|
if (result != BSEC_OK) {
|
||
|
|
ERROR("BSEC: %u Shadowing Error %i\n", word, result);
|
||
|
|
return result;
|
||
|
|
}
|
||
|
|
|
||
|
|
result = bsec_read_otp(otp_value, word);
|
||
|
|
if (result != BSEC_OK) {
|
||
|
|
ERROR("BSEC: %u Read Error %i\n", word, result);
|
||
|
|
}
|
||
|
|
|
||
|
|
return result;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* bsec_check_nsec_access_rights: check non-secure access rights to target OTP.
|
||
|
|
* otp: OTP number.
|
||
|
|
* return: BSEC_OK if authorized access.
|
||
|
|
*/
|
||
|
|
uint32_t bsec_check_nsec_access_rights(uint32_t otp)
|
||
|
|
{
|
||
|
|
#if defined(IMAGE_BL32)
|
||
|
|
if (otp > STM32MP1_OTP_MAX_ID) {
|
||
|
|
return BSEC_INVALID_PARAM;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (otp >= STM32MP1_UPPER_OTP_START) {
|
||
|
|
/* Check if BSEC is in OTP-SECURED closed_device state. */
|
||
|
|
if (stm32mp_is_closed_device()) {
|
||
|
|
if (!non_secure_can_access(otp)) {
|
||
|
|
return BSEC_ERROR;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
return BSEC_OK;
|
||
|
|
}
|
||
|
|
|