543 lines
14 KiB
C
543 lines
14 KiB
C
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/*
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* Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <string.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <lib/pmf/pmf.h>
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#include <lib/runtime_instr.h>
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#include <lib/smccc.h>
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#include <plat/common/platform.h>
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#include <services/arm_arch_svc.h>
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#include "psci_private.h"
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/*******************************************************************************
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* PSCI frontend api for servicing SMCs. Described in the PSCI spec.
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******************************************************************************/
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int psci_cpu_on(u_register_t target_cpu,
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uintptr_t entrypoint,
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u_register_t context_id)
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{
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int rc;
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entry_point_info_t ep;
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/* Determine if the cpu exists of not */
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rc = psci_validate_mpidr(target_cpu);
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if (rc != PSCI_E_SUCCESS)
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return PSCI_E_INVALID_PARAMS;
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/* Validate the entry point and get the entry_point_info */
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rc = psci_validate_entry_point(&ep, entrypoint, context_id);
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if (rc != PSCI_E_SUCCESS)
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return rc;
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/*
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* To turn this cpu on, specify which power
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* levels need to be turned on
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*/
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return psci_cpu_on_start(target_cpu, &ep);
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}
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unsigned int psci_version(void)
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{
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return PSCI_MAJOR_VER | PSCI_MINOR_VER;
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}
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int psci_cpu_suspend(unsigned int power_state,
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uintptr_t entrypoint,
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u_register_t context_id)
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{
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int rc;
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unsigned int target_pwrlvl, is_power_down_state;
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entry_point_info_t ep;
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psci_power_state_t state_info = { {PSCI_LOCAL_STATE_RUN} };
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plat_local_state_t cpu_pd_state;
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/* Validate the power_state parameter */
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rc = psci_validate_power_state(power_state, &state_info);
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if (rc != PSCI_E_SUCCESS) {
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assert(rc == PSCI_E_INVALID_PARAMS);
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return rc;
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}
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/*
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* Get the value of the state type bit from the power state parameter.
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*/
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is_power_down_state = psci_get_pstate_type(power_state);
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/* Sanity check the requested suspend levels */
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assert(psci_validate_suspend_req(&state_info, is_power_down_state)
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== PSCI_E_SUCCESS);
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target_pwrlvl = psci_find_target_suspend_lvl(&state_info);
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if (target_pwrlvl == PSCI_INVALID_PWR_LVL) {
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ERROR("Invalid target power level for suspend operation\n");
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panic();
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}
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/* Fast path for CPU standby.*/
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if (is_cpu_standby_req(is_power_down_state, target_pwrlvl)) {
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if (psci_plat_pm_ops->cpu_standby == NULL)
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return PSCI_E_INVALID_PARAMS;
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/*
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* Set the state of the CPU power domain to the platform
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* specific retention state and enter the standby state.
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*/
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cpu_pd_state = state_info.pwr_domain_state[PSCI_CPU_PWR_LVL];
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psci_set_cpu_local_state(cpu_pd_state);
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#if ENABLE_PSCI_STAT
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plat_psci_stat_accounting_start(&state_info);
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#endif
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#if ENABLE_RUNTIME_INSTRUMENTATION
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PMF_CAPTURE_TIMESTAMP(rt_instr_svc,
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RT_INSTR_ENTER_HW_LOW_PWR,
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PMF_NO_CACHE_MAINT);
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#endif
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psci_plat_pm_ops->cpu_standby(cpu_pd_state);
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/* Upon exit from standby, set the state back to RUN. */
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psci_set_cpu_local_state(PSCI_LOCAL_STATE_RUN);
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#if ENABLE_RUNTIME_INSTRUMENTATION
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PMF_CAPTURE_TIMESTAMP(rt_instr_svc,
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RT_INSTR_EXIT_HW_LOW_PWR,
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PMF_NO_CACHE_MAINT);
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#endif
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#if ENABLE_PSCI_STAT
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plat_psci_stat_accounting_stop(&state_info);
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/* Update PSCI stats */
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psci_stats_update_pwr_up(PSCI_CPU_PWR_LVL, &state_info);
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#endif
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return PSCI_E_SUCCESS;
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}
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/*
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* If a power down state has been requested, we need to verify entry
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* point and program entry information.
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*/
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if (is_power_down_state != 0U) {
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rc = psci_validate_entry_point(&ep, entrypoint, context_id);
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if (rc != PSCI_E_SUCCESS)
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return rc;
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}
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/*
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* Do what is needed to enter the power down state. Upon success,
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* enter the final wfi which will power down this CPU. This function
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* might return if the power down was abandoned for any reason, e.g.
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* arrival of an interrupt
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*/
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psci_cpu_suspend_start(&ep,
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target_pwrlvl,
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&state_info,
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is_power_down_state);
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return PSCI_E_SUCCESS;
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}
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int psci_system_suspend(uintptr_t entrypoint, u_register_t context_id)
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{
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int rc;
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psci_power_state_t state_info;
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entry_point_info_t ep;
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/* Check if the current CPU is the last ON CPU in the system */
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if (psci_is_last_on_cpu() == 0U)
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return PSCI_E_DENIED;
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/* Validate the entry point and get the entry_point_info */
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rc = psci_validate_entry_point(&ep, entrypoint, context_id);
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if (rc != PSCI_E_SUCCESS)
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return rc;
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/* Query the psci_power_state for system suspend */
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psci_query_sys_suspend_pwrstate(&state_info);
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/*
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* Check if platform allows suspend to Highest power level
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* (System level)
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*/
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if (psci_find_target_suspend_lvl(&state_info) < PLAT_MAX_PWR_LVL)
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return PSCI_E_DENIED;
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/* Ensure that the psci_power_state makes sense */
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assert(psci_validate_suspend_req(&state_info, PSTATE_TYPE_POWERDOWN)
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== PSCI_E_SUCCESS);
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assert(is_local_state_off(
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state_info.pwr_domain_state[PLAT_MAX_PWR_LVL]) != 0);
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/*
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* Do what is needed to enter the system suspend state. This function
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* might return if the power down was abandoned for any reason, e.g.
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* arrival of an interrupt
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*/
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psci_cpu_suspend_start(&ep,
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PLAT_MAX_PWR_LVL,
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&state_info,
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PSTATE_TYPE_POWERDOWN);
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return PSCI_E_SUCCESS;
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}
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int psci_cpu_off(void)
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{
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int rc;
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unsigned int target_pwrlvl = PLAT_MAX_PWR_LVL;
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/*
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* Do what is needed to power off this CPU and possible higher power
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* levels if it able to do so. Upon success, enter the final wfi
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* which will power down this CPU.
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*/
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rc = psci_do_cpu_off(target_pwrlvl);
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/*
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* The only error cpu_off can return is E_DENIED. So check if that's
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* indeed the case.
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*/
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assert(rc == PSCI_E_DENIED);
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return rc;
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}
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int psci_affinity_info(u_register_t target_affinity,
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unsigned int lowest_affinity_level)
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{
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int target_idx;
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/* We dont support level higher than PSCI_CPU_PWR_LVL */
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if (lowest_affinity_level > PSCI_CPU_PWR_LVL)
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return PSCI_E_INVALID_PARAMS;
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/* Calculate the cpu index of the target */
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target_idx = plat_core_pos_by_mpidr(target_affinity);
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if (target_idx == -1)
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return PSCI_E_INVALID_PARAMS;
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/*
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* Generic management:
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* Perform cache maintanence ahead of reading the target CPU state to
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* ensure that the data is not stale.
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* There is a theoretical edge case where the cache may contain stale
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* data for the target CPU data - this can occur under the following
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* conditions:
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* - the target CPU is in another cluster from the current
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* - the target CPU was the last CPU to shutdown on its cluster
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* - the cluster was removed from coherency as part of the CPU shutdown
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*
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* In this case the cache maintenace that was performed as part of the
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* target CPUs shutdown was not seen by the current CPU's cluster. And
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* so the cache may contain stale data for the target CPU.
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*/
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flush_cpu_data_by_index((unsigned int)target_idx,
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psci_svc_cpu_data.aff_info_state);
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return psci_get_aff_info_state_by_idx(target_idx);
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}
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int psci_migrate(u_register_t target_cpu)
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{
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int rc;
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u_register_t resident_cpu_mpidr;
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rc = psci_spd_migrate_info(&resident_cpu_mpidr);
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if (rc != PSCI_TOS_UP_MIG_CAP)
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return (rc == PSCI_TOS_NOT_UP_MIG_CAP) ?
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PSCI_E_DENIED : PSCI_E_NOT_SUPPORTED;
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/*
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* Migrate should only be invoked on the CPU where
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* the Secure OS is resident.
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*/
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if (resident_cpu_mpidr != read_mpidr_el1())
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return PSCI_E_NOT_PRESENT;
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/* Check the validity of the specified target cpu */
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rc = psci_validate_mpidr(target_cpu);
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if (rc != PSCI_E_SUCCESS)
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return PSCI_E_INVALID_PARAMS;
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assert((psci_spd_pm != NULL) && (psci_spd_pm->svc_migrate != NULL));
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rc = psci_spd_pm->svc_migrate(read_mpidr_el1(), target_cpu);
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assert((rc == PSCI_E_SUCCESS) || (rc == PSCI_E_INTERN_FAIL));
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return rc;
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}
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int psci_migrate_info_type(void)
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{
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u_register_t resident_cpu_mpidr;
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return psci_spd_migrate_info(&resident_cpu_mpidr);
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}
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u_register_t psci_migrate_info_up_cpu(void)
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{
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u_register_t resident_cpu_mpidr;
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int rc;
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/*
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* Return value of this depends upon what
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* psci_spd_migrate_info() returns.
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*/
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rc = psci_spd_migrate_info(&resident_cpu_mpidr);
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if ((rc != PSCI_TOS_NOT_UP_MIG_CAP) && (rc != PSCI_TOS_UP_MIG_CAP))
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return (u_register_t)(register_t) PSCI_E_INVALID_PARAMS;
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return resident_cpu_mpidr;
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}
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int psci_node_hw_state(u_register_t target_cpu,
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unsigned int power_level)
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{
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int rc;
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/* Validate target_cpu */
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rc = psci_validate_mpidr(target_cpu);
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if (rc != PSCI_E_SUCCESS)
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return PSCI_E_INVALID_PARAMS;
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/* Validate power_level against PLAT_MAX_PWR_LVL */
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if (power_level > PLAT_MAX_PWR_LVL)
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return PSCI_E_INVALID_PARAMS;
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/*
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* Dispatch this call to platform to query power controller, and pass on
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* to the caller what it returns
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*/
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assert(psci_plat_pm_ops->get_node_hw_state != NULL);
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rc = psci_plat_pm_ops->get_node_hw_state(target_cpu, power_level);
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assert(((rc >= HW_ON) && (rc <= HW_STANDBY))
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|| (rc == PSCI_E_NOT_SUPPORTED)
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|| (rc == PSCI_E_INVALID_PARAMS));
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return rc;
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}
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int psci_features(unsigned int psci_fid)
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{
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unsigned int local_caps = psci_caps;
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if (psci_fid == SMCCC_VERSION)
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return PSCI_E_SUCCESS;
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/* Check if it is a 64 bit function */
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if (((psci_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_64)
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local_caps &= PSCI_CAP_64BIT_MASK;
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/* Check for invalid fid */
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if (!(is_std_svc_call(psci_fid) && is_valid_fast_smc(psci_fid)
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&& is_psci_fid(psci_fid)))
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return PSCI_E_NOT_SUPPORTED;
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/* Check if the psci fid is supported or not */
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if ((local_caps & define_psci_cap(psci_fid)) == 0U)
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return PSCI_E_NOT_SUPPORTED;
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/* Format the feature flags */
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if ((psci_fid == PSCI_CPU_SUSPEND_AARCH32) ||
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(psci_fid == PSCI_CPU_SUSPEND_AARCH64)) {
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/*
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* The trusted firmware does not support OS Initiated Mode.
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*/
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unsigned int ret = ((FF_PSTATE << FF_PSTATE_SHIFT) |
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(((FF_SUPPORTS_OS_INIT_MODE == 1U) ? 0U : 1U)
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<< FF_MODE_SUPPORT_SHIFT));
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return (int) ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Return 0 for all other fid's */
|
||
|
|
return PSCI_E_SUCCESS;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*******************************************************************************
|
||
|
|
* PSCI top level handler for servicing SMCs.
|
||
|
|
******************************************************************************/
|
||
|
|
u_register_t psci_smc_handler(uint32_t smc_fid,
|
||
|
|
u_register_t x1,
|
||
|
|
u_register_t x2,
|
||
|
|
u_register_t x3,
|
||
|
|
u_register_t x4,
|
||
|
|
void *cookie,
|
||
|
|
void *handle,
|
||
|
|
u_register_t flags)
|
||
|
|
{
|
||
|
|
u_register_t ret;
|
||
|
|
|
||
|
|
if (is_caller_secure(flags))
|
||
|
|
return (u_register_t)SMC_UNK;
|
||
|
|
|
||
|
|
/* Check the fid against the capabilities */
|
||
|
|
if ((psci_caps & define_psci_cap(smc_fid)) == 0U)
|
||
|
|
return (u_register_t)SMC_UNK;
|
||
|
|
|
||
|
|
if (((smc_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_32) {
|
||
|
|
/* 32-bit PSCI function, clear top parameter bits */
|
||
|
|
|
||
|
|
uint32_t r1 = (uint32_t)x1;
|
||
|
|
uint32_t r2 = (uint32_t)x2;
|
||
|
|
uint32_t r3 = (uint32_t)x3;
|
||
|
|
|
||
|
|
switch (smc_fid) {
|
||
|
|
case PSCI_VERSION:
|
||
|
|
ret = (u_register_t)psci_version();
|
||
|
|
break;
|
||
|
|
|
||
|
|
case PSCI_CPU_OFF:
|
||
|
|
ret = (u_register_t)psci_cpu_off();
|
||
|
|
break;
|
||
|
|
|
||
|
|
case PSCI_CPU_SUSPEND_AARCH32:
|
||
|
|
ret = (u_register_t)psci_cpu_suspend(r1, r2, r3);
|
||
|
|
break;
|
||
|
|
|
||
|
|
case PSCI_CPU_ON_AARCH32:
|
||
|
|
ret = (u_register_t)psci_cpu_on(r1, r2, r3);
|
||
|
|
break;
|
||
|
|
|
||
|
|
case PSCI_AFFINITY_INFO_AARCH32:
|
||
|
|
ret = (u_register_t)psci_affinity_info(r1, r2);
|
||
|
|
break;
|
||
|
|
|
||
|
|
case PSCI_MIG_AARCH32:
|
||
|
|
ret = (u_register_t)psci_migrate(r1);
|
||
|
|
break;
|
||
|
|
|
||
|
|
case PSCI_MIG_INFO_TYPE:
|
||
|
|
ret = (u_register_t)psci_migrate_info_type();
|
||
|
|
break;
|
||
|
|
|
||
|
|
case PSCI_MIG_INFO_UP_CPU_AARCH32:
|
||
|
|
ret = psci_migrate_info_up_cpu();
|
||
|
|
break;
|
||
|
|
|
||
|
|
case PSCI_NODE_HW_STATE_AARCH32:
|
||
|
|
ret = (u_register_t)psci_node_hw_state(r1, r2);
|
||
|
|
break;
|
||
|
|
|
||
|
|
case PSCI_SYSTEM_SUSPEND_AARCH32:
|
||
|
|
ret = (u_register_t)psci_system_suspend(r1, r2);
|
||
|
|
break;
|
||
|
|
|
||
|
|
case PSCI_SYSTEM_OFF:
|
||
|
|
psci_system_off();
|
||
|
|
/* We should never return from psci_system_off() */
|
||
|
|
break;
|
||
|
|
|
||
|
|
case PSCI_SYSTEM_RESET:
|
||
|
|
psci_system_reset();
|
||
|
|
/* We should never return from psci_system_reset() */
|
||
|
|
break;
|
||
|
|
|
||
|
|
case PSCI_FEATURES:
|
||
|
|
ret = (u_register_t)psci_features(r1);
|
||
|
|
break;
|
||
|
|
|
||
|
|
#if ENABLE_PSCI_STAT
|
||
|
|
case PSCI_STAT_RESIDENCY_AARCH32:
|
||
|
|
ret = psci_stat_residency(r1, r2);
|
||
|
|
break;
|
||
|
|
|
||
|
|
case PSCI_STAT_COUNT_AARCH32:
|
||
|
|
ret = psci_stat_count(r1, r2);
|
||
|
|
break;
|
||
|
|
#endif
|
||
|
|
case PSCI_MEM_PROTECT:
|
||
|
|
ret = psci_mem_protect(r1);
|
||
|
|
break;
|
||
|
|
|
||
|
|
case PSCI_MEM_CHK_RANGE_AARCH32:
|
||
|
|
ret = psci_mem_chk_range(r1, r2);
|
||
|
|
break;
|
||
|
|
|
||
|
|
case PSCI_SYSTEM_RESET2_AARCH32:
|
||
|
|
/* We should never return from psci_system_reset2() */
|
||
|
|
ret = psci_system_reset2(r1, r2);
|
||
|
|
break;
|
||
|
|
|
||
|
|
default:
|
||
|
|
WARN("Unimplemented PSCI Call: 0x%x\n", smc_fid);
|
||
|
|
ret = (u_register_t)SMC_UNK;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
} else {
|
||
|
|
/* 64-bit PSCI function */
|
||
|
|
|
||
|
|
switch (smc_fid) {
|
||
|
|
case PSCI_CPU_SUSPEND_AARCH64:
|
||
|
|
ret = (u_register_t)
|
||
|
|
psci_cpu_suspend((unsigned int)x1, x2, x3);
|
||
|
|
break;
|
||
|
|
|
||
|
|
case PSCI_CPU_ON_AARCH64:
|
||
|
|
ret = (u_register_t)psci_cpu_on(x1, x2, x3);
|
||
|
|
break;
|
||
|
|
|
||
|
|
case PSCI_AFFINITY_INFO_AARCH64:
|
||
|
|
ret = (u_register_t)
|
||
|
|
psci_affinity_info(x1, (unsigned int)x2);
|
||
|
|
break;
|
||
|
|
|
||
|
|
case PSCI_MIG_AARCH64:
|
||
|
|
ret = (u_register_t)psci_migrate(x1);
|
||
|
|
break;
|
||
|
|
|
||
|
|
case PSCI_MIG_INFO_UP_CPU_AARCH64:
|
||
|
|
ret = psci_migrate_info_up_cpu();
|
||
|
|
break;
|
||
|
|
|
||
|
|
case PSCI_NODE_HW_STATE_AARCH64:
|
||
|
|
ret = (u_register_t)psci_node_hw_state(
|
||
|
|
x1, (unsigned int) x2);
|
||
|
|
break;
|
||
|
|
|
||
|
|
case PSCI_SYSTEM_SUSPEND_AARCH64:
|
||
|
|
ret = (u_register_t)psci_system_suspend(x1, x2);
|
||
|
|
break;
|
||
|
|
|
||
|
|
#if ENABLE_PSCI_STAT
|
||
|
|
case PSCI_STAT_RESIDENCY_AARCH64:
|
||
|
|
ret = psci_stat_residency(x1, (unsigned int) x2);
|
||
|
|
break;
|
||
|
|
|
||
|
|
case PSCI_STAT_COUNT_AARCH64:
|
||
|
|
ret = psci_stat_count(x1, (unsigned int) x2);
|
||
|
|
break;
|
||
|
|
#endif
|
||
|
|
|
||
|
|
case PSCI_MEM_CHK_RANGE_AARCH64:
|
||
|
|
ret = psci_mem_chk_range(x1, x2);
|
||
|
|
break;
|
||
|
|
|
||
|
|
case PSCI_SYSTEM_RESET2_AARCH64:
|
||
|
|
/* We should never return from psci_system_reset2() */
|
||
|
|
ret = psci_system_reset2((uint32_t) x1, x2);
|
||
|
|
break;
|
||
|
|
|
||
|
|
default:
|
||
|
|
WARN("Unimplemented PSCI Call: 0x%x\n", smc_fid);
|
||
|
|
ret = (u_register_t)SMC_UNK;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|