63 lines
1.6 KiB
C
63 lines
1.6 KiB
C
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/* Copyright 2014 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* Veyron board-specific configuration */
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#include "battery.h"
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#include "chipset.h"
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#include "common.h"
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#include "extpower.h"
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#include "gpio.h"
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#include "i2c.h"
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#include "keyboard_raw.h"
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#include "lid_switch.h"
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#include "power.h"
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#include "power_button.h"
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#include "power.h"
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#include "pwm.h"
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#include "pwm_chip.h"
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#include "registers.h"
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#include "spi.h"
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#include "task.h"
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#include "util.h"
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#include "timer.h"
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#include "charger.h"
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#include "gpio_list.h"
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/* power signal list. Must match order of enum power_signal. */
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const struct power_signal_info power_signal_list[] = {
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{GPIO_SOC_POWER_GOOD, POWER_SIGNAL_ACTIVE_HIGH, "POWER_GOOD"},
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{GPIO_SUSPEND_L, POWER_SIGNAL_ACTIVE_HIGH, "SUSPEND#_ASSERTED"},
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};
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BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
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/* I2C ports */
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const struct i2c_port_t i2c_ports[] = {
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{"master", I2C_PORT_MASTER, 100},
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};
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const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
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/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
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const struct pwm_t pwm_channels[] = {
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{STM32_TIM(2), STM32_TIM_CH(3),
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PWM_CONFIG_ACTIVE_LOW},
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};
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BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
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void board_config_pre_init(void)
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{
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/* enable SYSCFG clock */
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STM32_RCC_APB2ENR |= BIT(0);
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/* Remap USART DMA to match the USART driver */
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/*
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* the DMA mapping is :
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* Chan 2 : TIM1_CH1
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* Chan 3 : SPI1_TX
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* Chan 4 : USART1_TX
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* Chan 5 : USART1_RX
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*/
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STM32_SYSCFG_CFGR1 |= BIT(9) | BIT(10); /* Remap USART1 RX/TX DMA */
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}
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