144 lines
4.0 KiB
C
144 lines
4.0 KiB
C
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/* Copyright 2017 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* Configuration for Nuvoton M4 EB */
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#ifndef __CROS_EC_BOARD_H
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#define __CROS_EC_BOARD_H
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/*
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* npcx7 EVB version:
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* 1 - for EVB version 1 which supports npcx7m6g
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* 2 - for EVB version 2 which supports npcx7m6f/npcx7m6fb/npcx7m6fc/npcx7m7wb
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*/
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#if defined(CHIP_VARIANT_NPCX7M6G)
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#define BOARD_VERSION 1
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#elif defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6FB) || \
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defined(CHIP_VARIANT_NPCX7M6FC) || defined(CHIP_VARIANT_NPCX7M7WB) || \
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defined(CHIP_VARIANT_NPCX7M7WC)
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#define BOARD_VERSION 2
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#endif
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/* EC modules */
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#define CONFIG_ADC
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#define CONFIG_PWM
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#define CONFIG_SPI
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#define CONFIG_I2C
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/* Features of eSPI */
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#define CONFIG_HOSTCMD_ESPI
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#define CONFIG_HOSTCMD_ESPI_VW_SLP_SIGNALS /* Use VW signals instead of GPIOs */
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/* Optional features */
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#define CONFIG_ENABLE_JTAG_SELECTION
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#define CONFIG_BOARD_VERSION_GPIO
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#define CONFIG_EXTPOWER_GPIO
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#define CONFIG_I2C_MASTER
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#define CONFIG_KEYBOARD_BOARD_CONFIG
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#define CONFIG_KEYBOARD_PROTOCOL_8042
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#undef CONFIG_LOW_POWER_IDLE /* Deep Sleep Support */
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#define CONFIG_POWER_BUTTON
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#undef CONFIG_PSTORE
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#define CONFIG_PWM_KBLIGHT
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#define CONFIG_VBOOT_HASH
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#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands */
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/* EC console commands */
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#define CONFIG_CMD_TASKREADY
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#define CONFIG_CMD_STACKOVERFLOW
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#define CONFIG_CMD_JUMPTAGS
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#define CONFIG_CMD_FLASH
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#define CONFIG_CMD_SPI_FLASH
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#define CONFIG_CMD_SCRATCHPAD
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#define CONFIG_CMD_I2CWEDGE
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/* I2C port for CONFIG_CMD_I2CWEDGE */
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#define I2C_PORT_MASTER NPCX_I2C_PORT0_0
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#define I2C_PORT_HOST 0
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/* Fans for testing */
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#define CONFIG_FANS 1
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/* Internal spi-flash on npcx7 ec */
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#define CONFIG_SPI_FLASH_PORT 0
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#define CONFIG_SPI_FLASH
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#define CONFIG_SPI_FLASH_REGS
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#if defined(CHIP_VARIANT_NPCX7M6FC) || defined(CHIP_VARIANT_NPCX7M7WC)
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#define CONFIG_SPI_FLASH_W25Q40 /* Internal spi flash type */
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#define CONFIG_FLASH_SIZE 0x00080000 /* 512 KB internal spi flash */
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#else
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#define CONFIG_SPI_FLASH_W25Q80 /* Internal spi flash type */
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#define CONFIG_FLASH_SIZE 0x00100000 /* 1 MB internal spi flash */
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#endif
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/* New features on npcx7 ec */
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#define CONFIG_KEYBOARD_KSO_HIGH_DRIVE /* Quasi-bidirectional buf for KSOs */
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#if (BOARD_VERSION == 2)
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#define CONFIG_HIBERNATE_PSL /* Use PSL (Power Switch Logic) for hibernate */
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#define CONFIG_CLOCK_SRC_EXTERNAL /* Use external 32kHz OSC as LFCLK source */
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#if defined(CHIP_VARIANT_NPCX7M7WB) || defined(CHIP_VARIANT_NPCX7M7WC)
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#define CONFIG_WAKE_ON_VOICE /* Use Audio front-end for Wake-on-Voice */
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#endif
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#undef CONFIG_FANS /* Remove fan application */
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#define CONFIG_FANS 0
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#else
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#undef CONFIG_HIBERNATE_PSL /* Use PSL (Power Switch Logic) for hibernate */
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#undef CONFIG_CLOCK_SRC_EXTERNAL /* Use external 32kHz OSC as LFCLK source */
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#endif
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/* Optional feature to configure npcx7 chip */
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/* Select which UART Controller is the Console UART */
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#undef CONFIG_CONSOLE_UART
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#define CONFIG_CONSOLE_UART 0 /* 0:UART1 1:UART2 */
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/*
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* This definition below actually doesn't define which UART controller to be
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* used. Instead, it defines which pinouts (GPIO10/11 or GPIO64/65) are
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* connected to "UART1" controller.
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*/
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#if (BOARD_VERSION == 2)
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#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 as UART1 */
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#else
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#define NPCX_UART_MODULE2 0 /* 0:GPIO10/11 as UART1 */
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#endif
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#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 1:GPIOD5/E2/D4/E5 as JTAG */
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#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
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#define NPCX7_PWM1_SEL 0 /* 0:GPIOC2 as I2CSCL0 1:as PWM1 (only in npcx7) */
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#ifndef __ASSEMBLER__
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enum adc_channel {
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ADC_CH_0 = 0,
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ADC_CH_1,
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ADC_CH_2,
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ADC_CH_3,
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ADC_CH_4,
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ADC_CH_COUNT
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};
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enum pwm_channel {
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PWM_CH_FAN,
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PWM_CH_KBLIGHT,
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/* Number of PWM channels */
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PWM_CH_COUNT
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};
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enum fan_channel {
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FAN_CH_0,
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/* Number of FAN channels */
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FAN_CH_COUNT
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};
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enum mft_channel {
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MFT_CH_0,
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/* Number of MFT channels */
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MFT_CH_COUNT
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};
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#include "gpio_signal.h"
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#endif /* !__ASSEMBLER__ */
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#endif /* __CROS_EC_BOARD_H */
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