119 lines
3.9 KiB
C
119 lines
3.9 KiB
C
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/* Copyright 2016 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#ifndef __CROS_EC_CONFIG_CHIP_H
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#define __CROS_EC_CONFIG_CHIP_H
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/* CPU core BFD configuration */
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#include "core/minute-ia/config_core.h"
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#ifndef __ASSEMBLER__
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/* Needed for PANIC_DATA_BASE */
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#include "ish_persistent_data.h"
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#endif
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/* Number of IRQ vectors on the ISH */
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#define CONFIG_IRQ_COUNT (VEC_TO_IRQ(255) + 1)
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/* Use a bigger console output buffer */
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#undef CONFIG_UART_TX_BUF_SIZE
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#define CONFIG_UART_TX_BUF_SIZE 2048
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/* Interval between HOOK_TICK notifications */
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#define HOOK_TICK_INTERVAL_MS 250
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#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC)
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/* Maximum number of deferrable functions */
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#define DEFERRABLE_MAX_COUNT 8
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/* this macro causes 'pause' and reduces loop counts inside loop. */
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#define CPU_RELAX() asm volatile("rep; nop" ::: "memory")
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/*****************************************************************************/
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/* Memory Layout */
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/*****************************************************************************/
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#define CONFIG_RAM_BASE 0xFF000000
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#define CONFIG_RAM_SIZE 0x000A0000
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#define CONFIG_RAM_BANK_SIZE 0x00008000
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#if defined(CHIP_FAMILY_ISH3)
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/* On ISH3, there is no separate AON memory; use last 4KB of SRAM */
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#define CONFIG_AON_RAM_BASE 0xFF09F000
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#define CONFIG_AON_RAM_SIZE 0x00001000
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#elif defined(CHIP_FAMILY_ISH4)
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#define CONFIG_AON_RAM_BASE 0xFF800000
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#define CONFIG_AON_RAM_SIZE 0x00001000
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#elif defined(CHIP_FAMILY_ISH5)
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#define CONFIG_AON_RAM_BASE 0xFF800000
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#define CONFIG_AON_RAM_SIZE 0x00002000
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#else
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#error "CHIP_FAMILY_ISH(3|4|5) must be defined"
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#endif
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/* The end of the AON memory is reserved for read-only use */
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#define CONFIG_AON_PERSISTENT_SIZE 0x180
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#define CONFIG_AON_PERSISTENT_BASE (CONFIG_AON_RAM_BASE \
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+ CONFIG_AON_RAM_SIZE \
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- CONFIG_AON_PERSISTENT_SIZE)
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/* Store persistent panic data in AON memory. */
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#define CONFIG_PANIC_DATA_BASE (&(ish_persistent_data.panic_data))
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/* System stack size */
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#define CONFIG_STACK_SIZE 1024
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/* non-standard task stack sizes */
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#define IDLE_TASK_STACK_SIZE 640
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#define LARGER_TASK_STACK_SIZE 1024
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#define HUGE_TASK_STACK_SIZE 2048
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/* Default task stack size */
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#define TASK_STACK_SIZE 640
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/****************************************************************************/
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/* Define our flash layout. */
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/* Note: The 4 macros below are unnecesasry for the ISH chip. However they are
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* referenced in common files and hence retained to avoid build errors.
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*/
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/* Protect bank size 4K bytes */
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#define CONFIG_FLASH_BANK_SIZE 0x00001000
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/* Sector erase size 4K bytes */
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#define CONFIG_FLASH_ERASE_SIZE 0x00000000
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/* Minimum write size */
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#define CONFIG_FLASH_WRITE_SIZE 0x00000000
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/* Program memory base address */
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#define CONFIG_PROGRAM_MEMORY_BASE 0x00100000
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#include "config_flash_layout.h"
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/*****************************************************************************/
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/* Watchdog Timer Configuration */
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/*****************************************************************************/
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#if defined(CHIP_FAMILY_ISH3) || defined(CHIP_FAMILY_ISH5)
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#define WDT_CLOCK_HZ (120000000) /* 120 MHz */
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#elif defined(CHIP_FAMILY_ISH4)
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#define WDT_CLOCK_HZ (100000000) /* 100 MHz */
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#else
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#error "CHIP_FAMILY_ISH(3|4|5) must be defined"
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#endif
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/* Provide WDT vec number to Minute-IA core implementation */
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#undef CONFIG_MIA_WDT_VEC
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#define CONFIG_MIA_WDT_VEC ISH_WDT_VEC
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/****************************************************************************/
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/* Customize the build */
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/* Optional features present on this chip */
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/* ISH uses 64-bit hardware timer */
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#define CONFIG_HWTIMER_64BIT
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/* Macro used with gpio.inc, ISH only has port 0 */
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#define GPIO_PIN(index) 0, (1 << (index))
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#define GPIO_PIN_MASK(m) .port = 0, .mask = (m)
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#endif /* __CROS_EC_CONFIG_CHIP_H */
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