266 lines
7.0 KiB
C
266 lines
7.0 KiB
C
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/* Copyright 2016 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* Hardware timers driver for ISH High Precision Event Timers (HPET) */
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#include "console.h"
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#include "hpet.h"
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#include "hwtimer.h"
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#include "timer.h"
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#include "registers.h"
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#include "task.h"
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#include "util.h"
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#define CPUTS(outstr) cputs(CC_CLOCK, outstr)
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#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
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#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ## args)
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static uint32_t last_deadline;
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/*
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* The ISH hardware needs at least 25 ticks of leeway to arms the timer.
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* ISH4/5 are the slowest with 32kHz timers, so we wait at least 800us when
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* scheduling events in the future
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*/
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#define MINIMUM_EVENT_DELAY_US 800
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/*
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* ISH HPET timer HW has latency for interrupt, on ISH5, this latency is about
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* 3 ticks, defined this configuration to calibrate the 'last_deadline' which is
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* updated in event timer interrupt ISR. Without this calibration, we could
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* get negative sleep time in idle task for low power sleep process.
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*/
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#define HPET_INT_LATENCY_TICKS 3
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/* Scaling helper methods for different ISH chip variants */
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#ifdef CHIP_FAMILY_ISH3
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#define CLOCK_FACTOR 12
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BUILD_ASSERT(CLOCK_FACTOR * SECOND == ISH_HPET_CLK_FREQ);
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static inline uint64_t scale_us2ticks(uint64_t us)
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{
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return us * CLOCK_FACTOR;
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}
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static inline uint32_t scale_us2ticks_32(uint32_t us)
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{
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/* no optimization for ISH3 */
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return us * CLOCK_FACTOR;
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}
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static inline uint64_t scale_ticks2us(uint64_t ticks)
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{
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return ticks / CLOCK_FACTOR;
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}
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static inline void wait_while_settling(uint32_t mask)
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{
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/* Do nothing on ISH3, only ISH4 and ISH5 need settling */
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}
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#elif defined(CHIP_FAMILY_ISH4) || defined(CHIP_FAMILY_ISH5)
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#define CLOCK_SCALE_BITS 15
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BUILD_ASSERT(BIT(CLOCK_SCALE_BITS) == ISH_HPET_CLK_FREQ);
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/* Slow version, for 64-bit precision */
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static inline uint64_t scale_us2ticks(uint64_t us)
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{
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/* ticks = us * ISH_HPET_CLK_FREQ / SECOND */
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return (us << CLOCK_SCALE_BITS) / SECOND;
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}
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/* Fast version, for 32-bit precision */
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static inline uint32_t scale_us2ticks_32(uint32_t us)
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{
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/*
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* GCC optimizes this shift/divide into multiplication by a
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* magic number
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*/
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return (us << CLOCK_SCALE_BITS) / SECOND;
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}
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static inline uint64_t scale_ticks2us(uint64_t ticks)
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{
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return (ticks * SECOND) >> CLOCK_SCALE_BITS;
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}
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/*
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* HPET Control & Status register may indicate that a value which has
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* been written still needs propogated by hardware. Before updating
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* HPET_TIMER_CONF_CAP(N), be sure to wait on the value settling with
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* the corresponding mask (see hpet.h).
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*/
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static inline void wait_while_settling(uint32_t mask)
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{
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/* Wait for timer settings to settle ~ 150us */
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while (HPET_CTRL_STATUS & mask)
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continue;
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}
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#else
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#error "Must define CHIP_FAMILY_ISH(3|4|5)"
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#endif
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/*
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* The 64-bit read on a 32-bit chip can tear during the read. Ensure that the
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* value returned for 64-bit didn't rollover while we were reading it.
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*/
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static inline uint64_t read_main_timer(void)
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{
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timestamp_t t;
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uint32_t hi;
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/* need check main counter if valid when exit low power TCG mode */
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wait_while_settling(HPET_MAIN_COUNTER_VALID);
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do {
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t.le.hi = HPET_MAIN_COUNTER_64_HI;
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t.le.lo = HPET_MAIN_COUNTER_64_LO;
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hi = HPET_MAIN_COUNTER_64_HI;
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} while (t.le.hi != hi);
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return t.val;
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}
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void __hw_clock_event_set(uint32_t deadline)
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{
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uint32_t remaining_us;
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uint32_t current_us;
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uint64_t current_ticks;
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/* 'current_ticks' is the current absolute 64bit HW timer counter */
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current_ticks = read_main_timer();
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/*
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* 'current_us' is the low 32bit part of current time in 64bit micro
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* seconds format, it's can express 2^32 micro seconds in maximum.
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*/
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current_us = scale_ticks2us(current_ticks);
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/*
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* To ensure HW has enough time to react to the new timer value,
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* we make remaining time not less than 'MINIMUM_EVENT_DELAY_US'
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*/
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remaining_us = deadline - current_us;
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remaining_us = MAX(remaining_us, MINIMUM_EVENT_DELAY_US);
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/*
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* Set new 64bit absolute timeout ticks to Timer 1 comparator
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* register.
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* For ISH3, this assumes that remaining_us is less than 360 seconds
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* (2^32 us / 12Mhz), otherwise we would need to handle 32-bit rollover
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* of 12Mhz timer comparator value. Watchdog refresh happens at least
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* every 10 seconds.
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*/
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wait_while_settling(HPET_T1_CMP_SETTLING);
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HPET_TIMER_COMP(1) = current_ticks + scale_us2ticks_32(remaining_us);
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/*
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* Update 'last_deadline' and add calibrate delta due to HPET timer
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* interrupt latency.
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*/
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last_deadline = current_us + remaining_us;
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last_deadline += scale_ticks2us(HPET_INT_LATENCY_TICKS);
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/* Enable timer interrupt */
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wait_while_settling(HPET_T1_SETTLING);
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HPET_TIMER_CONF_CAP(1) |= HPET_Tn_INT_ENB_CNF;
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}
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uint32_t __hw_clock_event_get(void)
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{
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return last_deadline;
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}
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void __hw_clock_event_clear(void)
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{
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/*
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* We need to make sure that process_timers is called when the
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* event timer rolls over, set for deadline when
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* process_timers clears the event timer.
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*/
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__hw_clock_event_set(0xFFFFFFFF);
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}
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uint64_t __hw_clock_source_read64(void)
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{
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return scale_ticks2us(read_main_timer());
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}
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void __hw_clock_source_set64(uint64_t timestamp)
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{
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/* Reset both clock and overflow comparators */
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wait_while_settling(HPET_ANY_SETTLING);
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HPET_GENERAL_CONFIG &= ~HPET_ENABLE_CNF;
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HPET_MAIN_COUNTER_64 = scale_us2ticks(timestamp);
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wait_while_settling(HPET_ANY_SETTLING);
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HPET_GENERAL_CONFIG |= HPET_ENABLE_CNF;
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}
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static void hw_clock_event_isr(void)
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{
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/* Clear interrupt */
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wait_while_settling(HPET_INT_STATUS_SETTLING);
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HPET_INTR_CLEAR = BIT(1);
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process_timers(0);
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}
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DECLARE_IRQ(ISH_HPET_TIMER1_IRQ, hw_clock_event_isr);
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int __hw_clock_source_init64(uint64_t start_t)
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{
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/*
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* Timer 1 is used as an event timer. Timer 0 is unused, as
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* CONFIG_HWTIMER_64BIT is enabled.
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*/
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uint32_t timer1_config = 0x00000000;
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/* Disable HPET */
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wait_while_settling(HPET_ANY_SETTLING);
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HPET_GENERAL_CONFIG &= ~HPET_ENABLE_CNF;
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/* Disable T0 */
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HPET_TIMER_CONF_CAP(0) &= ~HPET_Tn_INT_ENB_CNF;
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/* Disable T1 until we get it set up (below) */
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HPET_TIMER_CONF_CAP(1) &= ~HPET_Tn_INT_ENB_CNF;
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/* Initialize main counter */
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HPET_MAIN_COUNTER_64 = scale_us2ticks(start_t);
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/* Clear any interrupts from previously running image */
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HPET_INTR_CLEAR = BIT(0);
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HPET_INTR_CLEAR = BIT(1);
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/* Timer 1 - IRQ routing */
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timer1_config &= ~HPET_Tn_INT_ROUTE_CNF_MASK;
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timer1_config |= (ISH_HPET_TIMER1_IRQ <<
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HPET_Tn_INT_ROUTE_CNF_SHIFT);
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/* Level triggered interrupt */
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timer1_config |= HPET_Tn_INT_TYPE_CNF;
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/* Initialize last_deadline until an event is scheduled */
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last_deadline = 0xFFFFFFFF;
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/* Before enabling, previous values must have settled */
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wait_while_settling(HPET_ANY_SETTLING);
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/* Unmask HPET IRQ in IOAPIC */
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task_enable_irq(ISH_HPET_TIMER1_IRQ);
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/* Copy timer config to hardware register */
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HPET_TIMER_CONF_CAP(1) |= timer1_config;
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/* Enable HPET */
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HPET_GENERAL_CONFIG |= HPET_ENABLE_CNF;
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/* Return IRQ value for OS event timer */
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return ISH_HPET_TIMER1_IRQ;
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}
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