80 lines
2.0 KiB
C
80 lines
2.0 KiB
C
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/* Copyright 2019 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#ifndef __CROS_EC_ISH_DMA_H
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#define __CROS_EC_ISH_DMA_H
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/* DMA return codes */
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#define DMA_RC_OK 0 /* Success */
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#define DMA_RC_TO 1 /* Time out */
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#define DMA_RC_HW 2 /* HW error (OCP) */
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/* DMA channels */
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#define PAGING_CHAN 0
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#define KERNEL_CHAN 1
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#define DST_IS_DRAM BIT(0)
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#define SRC_IS_DRAM BIT(1)
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#define NON_SNOOP BIT(2)
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/* ISH5 and on */
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#define RS0 0x0
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#define RS3 0x3
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#define RS_SRC_OFFSET 3
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#define RS_DST_OFFSET 5
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#define PAGE_SIZE 4096
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/**
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* SRAM: ISH local static ram
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* UMA: Protected system DRAM region dedicated for ISH
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* HOST_DRAM: OS owned buffer in system DRAM
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*/
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enum dma_mode {
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SRAM_TO_SRAM = 0,
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SRAM_TO_UMA = DST_IS_DRAM | (RS3 << RS_DST_OFFSET),
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UMA_TO_SRAM = SRC_IS_DRAM | (RS3 << RS_SRC_OFFSET),
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HOST_DRAM_TO_SRAM = SRC_IS_DRAM | (RS0 << RS_SRC_OFFSET),
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SRAM_TO_HOST_DRAM = DST_IS_DRAM | (RS0 << RS_DST_OFFSET)
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};
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/* Disable DMA engine */
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void ish_dma_disable(void);
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/* Initialize DMA engine */
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void ish_dma_init(void);
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/**
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* Main DMA transfer function
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*
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* @param chan DMA channel
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* @param dst Destination address
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* @param src Source address
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* @param length Transfer size
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* @param mode Transfer mode
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* @return DMA_RC_OK, or non-zero if error.
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*/
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int ish_dma_copy(uint32_t chan, uint32_t dst, uint32_t src, uint32_t length,
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enum dma_mode mode);
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/**
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* Set upper 32 bits address for DRAM
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*
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* @param chan DMA channel
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* @param dst_msb Destination DRAM upper 32 bits address
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* @param src_msb Source DRAM upper 32 bits address
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*/
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void ish_dma_set_msb(uint32_t chan, uint32_t dst_msb, uint32_t src_msb);
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/**
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* Wait for DMA transfer finish
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*
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* @param chan DMA channel
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* @return DMA_RC_OK, or non-zero if error.
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*/
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int ish_wait_for_dma_done(uint32_t ch);
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/* Disable OCP (Open Core Protocol) fabric time out */
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void ish_dma_ocp_timeout_disable(void);
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#endif
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