315 lines
8.5 KiB
C
315 lines
8.5 KiB
C
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/* Copyright 2014 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* EC2I control module for IT83xx. */
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#include "common.h"
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#include "console.h"
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#include "ec2i_chip.h"
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#include "hooks.h"
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#include "registers.h"
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#include "task.h"
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#include "timer.h"
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#include "util.h"
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static const struct ec2i_t keyboard_settings[] = {
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/* Select logical device 06h(keyboard) */
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{HOST_INDEX_LDN, LDN_KBC_KEYBOARD},
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/* Set IRQ=01h for logical device */
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{HOST_INDEX_IRQNUMX, 0x01},
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/* Configure IRQTP for KBC. */
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#ifdef CONFIG_HOSTCMD_ESPI
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/*
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* Interrupt request type select (IRQTP) for KBC.
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* bit 1, 0: IRQ request is buffered and applied to SERIRQ
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* 1: IRQ request is inverted before being applied to SERIRQ
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* bit 0, 0: Edge triggered mode
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* 1: Level triggered mode
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*
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* SERIRQ# is by default deasserted level high. However, when using
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* eSPI, SERIRQ# is routed over virtual wire as interrupt event. As
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* per eSPI base spec (doc#327432), all virtual wire interrupt events
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* are deasserted level low. Thus, it is necessary to configure this
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* interrupt as inverted. ITE hardware takes care of routing the SERIRQ#
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* signal appropriately over eSPI / LPC depending upon the selected
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* mode.
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*
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* Additionally, this interrupt is configured as edge-triggered on the
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* host side. So, match the trigger mode on the EC side as well.
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*/
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{HOST_INDEX_IRQTP, 0x02},
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#endif
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/* Enable logical device */
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{HOST_INDEX_LDA, 0x01},
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};
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#ifdef CONFIG_IT83XX_ENABLE_MOUSE_DEVICE
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static const struct ec2i_t mouse_settings[] = {
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/* Select logical device 05h(mouse) */
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{HOST_INDEX_LDN, LDN_KBC_MOUSE},
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/* Set IRQ=0Ch for logical device */
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{HOST_INDEX_IRQNUMX, 0x0C},
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/* Enable logical device */
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{HOST_INDEX_LDA, 0x01},
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};
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#endif
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static const struct ec2i_t pm1_settings[] = {
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/* Select logical device 11h(PM1 ACPI) */
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{HOST_INDEX_LDN, LDN_PMC1},
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/* Set IRQ=00h for logical device */
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{HOST_INDEX_IRQNUMX, 0x00},
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/* Enable logical device */
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{HOST_INDEX_LDA, 0x01},
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};
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static const struct ec2i_t pm2_settings[] = {
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/* Select logical device 12h(PM2) */
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{HOST_INDEX_LDN, LDN_PMC2},
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/* I/O Port Base Address 200h/204h */
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{HOST_INDEX_IOBAD0_MSB, 0x02},
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{HOST_INDEX_IOBAD0_LSB, 0x00},
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{HOST_INDEX_IOBAD1_MSB, 0x02},
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{HOST_INDEX_IOBAD1_LSB, 0x04},
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/* Set IRQ=00h for logical device */
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{HOST_INDEX_IRQNUMX, 0x00},
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/* Enable logical device */
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{HOST_INDEX_LDA, 0x01},
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};
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static const struct ec2i_t smfi_settings[] = {
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/* Select logical device 0Fh(SMFI) */
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{HOST_INDEX_LDN, LDN_SMFI},
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/* H2RAM LPC I/O cycle Dxxx */
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{HOST_INDEX_DSLDC6, 0x00},
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/* Enable H2RAM LPC I/O cycle */
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{HOST_INDEX_DSLDC7, 0x01},
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/* Enable logical device */
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{HOST_INDEX_LDA, 0x01},
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};
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/*
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* PM3 is enabled and base address is set to 80h so that we are able to get an
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* interrupt when host outputs data to port 80.
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*/
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static const struct ec2i_t pm3_settings[] = {
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/* Select logical device 17h(PM3) */
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{HOST_INDEX_LDN, LDN_PMC3},
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/* I/O Port Base Address 80h */
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{HOST_INDEX_IOBAD0_MSB, 0x00},
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{HOST_INDEX_IOBAD0_LSB, 0x80},
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{HOST_INDEX_IOBAD1_MSB, 0x00},
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{HOST_INDEX_IOBAD1_LSB, 0x00},
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/* Set IRQ=00h for logical device */
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{HOST_INDEX_IRQNUMX, 0x00},
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/* Enable logical device */
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{HOST_INDEX_LDA, 0x01},
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};
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/*
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* This logical device is not enabled, however P80L* settings need to be
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* performed on this logical device to ensure that port80 BRAM index is
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* initialized correctly.
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*/
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static const struct ec2i_t rtct_settings[] = {
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/* Select logical device 10h(RTCT) */
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{HOST_INDEX_LDN, LDN_RTCT},
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/* P80L Begin Index */
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{HOST_INDEX_DSLDC4, P80L_P80LB},
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/* P80L End Index */
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{HOST_INDEX_DSLDC5, P80L_P80LE},
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/* P80L Current Index */
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{HOST_INDEX_DSLDC6, P80L_P80LC},
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};
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#ifdef CONFIG_UART_HOST
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static const struct ec2i_t uart2_settings[] = {
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/* Select logical device 2h(UART2) */
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{HOST_INDEX_LDN, LDN_UART2},
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/*
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* I/O port base address is 2F8h.
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* Host can use LPC I/O port 0x2F8 ~ 0x2FF to access UART2.
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* See specification 7.24.4 for more detial.
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*/
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{HOST_INDEX_IOBAD0_MSB, 0x02},
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{HOST_INDEX_IOBAD0_LSB, 0xF8},
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/* IRQ number is 3 */
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{HOST_INDEX_IRQNUMX, 0x03},
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/*
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* Interrupt Request Type Select
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* bit1, 0: IRQ request is buffered and applied to SERIRQ.
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* 1: IRQ request is inverted before being applied to SERIRQ.
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* bit0, 0: Edge triggered mode.
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* 1: Level triggered mode.
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*/
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{HOST_INDEX_IRQTP, 0x02},
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/* Enable logical device */
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{HOST_INDEX_LDA, 0x01},
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};
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#endif
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/* EC2I access index/data port */
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enum ec2i_access {
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/* index port */
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EC2I_ACCESS_INDEX = 0,
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/* data port */
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EC2I_ACCESS_DATA = 1,
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};
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enum ec2i_status_mask {
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/* 1: EC read-access is still processing. */
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EC2I_STATUS_CRIB = BIT(1),
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/* 1: EC write-access is still processing with IHD register. */
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EC2I_STATUS_CWIB = BIT(2),
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EC2I_STATUS_ALL = (EC2I_STATUS_CRIB | EC2I_STATUS_CWIB),
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};
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static int ec2i_wait_status_bit_cleared(enum ec2i_status_mask mask)
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{
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/* delay ~15.25us */
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IT83XX_GCTRL_WNCKR = 0;
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return (IT83XX_EC2I_IBCTL & mask);
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}
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static enum ec2i_message ec2i_write_pnpcfg(enum ec2i_access sel, uint8_t data)
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{
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int rv = EC_ERROR_UNKNOWN;
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/* bit1 : VCC power on */
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if (IT83XX_SWUC_SWCTL1 & BIT(1)) {
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/*
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* Wait that both CRIB and CWIB bits in IBCTL register
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* are cleared.
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*/
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rv = ec2i_wait_status_bit_cleared(EC2I_STATUS_ALL);
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if (!rv) {
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/* Set indirect host I/O offset. */
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IT83XX_EC2I_IHIOA = sel;
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/* Write the data to IHD register */
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IT83XX_EC2I_IHD = data;
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/* Enable EC access to the PNPCFG registers */
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IT83XX_EC2I_IBMAE |= BIT(0);
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/* bit0: EC to I-Bus access enabled. */
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IT83XX_EC2I_IBCTL |= BIT(0);
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/* Wait the CWIB bit in IBCTL cleared. */
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rv = ec2i_wait_status_bit_cleared(EC2I_STATUS_CWIB);
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/* Disable EC access to the PNPCFG registers. */
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IT83XX_EC2I_IBMAE &= ~BIT(0);
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/* Disable EC to I-Bus access. */
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IT83XX_EC2I_IBCTL &= ~BIT(0);
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}
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}
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return rv ? EC2I_WRITE_ERROR : EC2I_WRITE_SUCCESS;
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}
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static enum ec2i_message ec2i_read_pnpcfg(enum ec2i_access sel)
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{
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int rv = EC_ERROR_UNKNOWN;
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uint8_t ihd = 0;
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/* bit1 : VCC power on */
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if (IT83XX_SWUC_SWCTL1 & BIT(1)) {
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/*
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* Wait that both CRIB and CWIB bits in IBCTL register
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* are cleared.
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*/
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rv = ec2i_wait_status_bit_cleared(EC2I_STATUS_ALL);
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if (!rv) {
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/* Set indirect host I/O offset. */
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IT83XX_EC2I_IHIOA = sel;
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/* Enable EC access to the PNPCFG registers */
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IT83XX_EC2I_IBMAE |= BIT(0);
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/* bit1: a read-action */
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IT83XX_EC2I_IBCTL |= BIT(1);
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/* bit0: EC to I-Bus access enabled. */
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IT83XX_EC2I_IBCTL |= BIT(0);
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/* Wait the CRIB bit in IBCTL cleared. */
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rv = ec2i_wait_status_bit_cleared(EC2I_STATUS_CRIB);
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/* Read the data from IHD register */
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ihd = IT83XX_EC2I_IHD;
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/* Disable EC access to the PNPCFG registers. */
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IT83XX_EC2I_IBMAE &= ~BIT(0);
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/* Disable EC to I-Bus access. */
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IT83XX_EC2I_IBCTL &= ~BIT(0);
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}
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}
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return rv ? EC2I_READ_ERROR : (EC2I_READ_SUCCESS + ihd);
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}
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/* EC2I read */
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enum ec2i_message ec2i_read(enum host_pnpcfg_index index)
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{
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enum ec2i_message ret = EC2I_READ_ERROR;
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uint32_t int_mask = get_int_mask();
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/* critical section with interrupts off */
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interrupt_disable();
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/* Set index */
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if (ec2i_write_pnpcfg(EC2I_ACCESS_INDEX, index) == EC2I_WRITE_SUCCESS)
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/* read data port */
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ret = ec2i_read_pnpcfg(EC2I_ACCESS_DATA);
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/* restore interrupts */
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set_int_mask(int_mask);
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return ret;
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}
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/* EC2I write */
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enum ec2i_message ec2i_write(enum host_pnpcfg_index index, uint8_t data)
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{
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enum ec2i_message ret = EC2I_WRITE_ERROR;
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uint32_t int_mask = get_int_mask();
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/* critical section with interrupts off */
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interrupt_disable();
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/* Set index */
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if (ec2i_write_pnpcfg(EC2I_ACCESS_INDEX, index) == EC2I_WRITE_SUCCESS)
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/* Set data */
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ret = ec2i_write_pnpcfg(EC2I_ACCESS_DATA, data);
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/* restore interrupts */
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set_int_mask(int_mask);
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return ret;
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}
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static void pnpcfg_configure(const struct ec2i_t *settings, size_t entries)
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{
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size_t i;
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for (i = 0; i < entries; i++) {
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if (ec2i_write(settings[i].index_port, settings[i].data_port) ==
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EC2I_WRITE_ERROR) {
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ccprints("Failed to apply %d", i);
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break;
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}
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}
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}
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#define PNPCFG(_s) \
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pnpcfg_configure(_s##_settings, ARRAY_SIZE(_s##_settings))
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static void pnpcfg_init(void)
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{
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/* Host access is disabled */
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IT83XX_EC2I_LSIOHA |= 0x3;
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PNPCFG(keyboard);
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#ifdef CONFIG_IT83XX_ENABLE_MOUSE_DEVICE
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PNPCFG(mouse);
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#endif
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PNPCFG(pm1);
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PNPCFG(pm2);
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PNPCFG(smfi);
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PNPCFG(pm3);
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PNPCFG(rtct);
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#ifdef CONFIG_UART_HOST
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PNPCFG(uart2);
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#endif
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}
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DECLARE_HOOK(HOOK_INIT, pnpcfg_init, HOOK_PRIO_DEFAULT);
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