345 lines
8.9 KiB
C
345 lines
8.9 KiB
C
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/* Copyright 2019 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* I2C module for Chrome EC */
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#include "clock.h"
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#include "compile_time_macros.h"
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#include "console.h"
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#include "gpio.h"
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#include "hooks.h"
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#include "i2c_slave.h"
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#include "registers.h"
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#include <stddef.h>
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#include <string.h>
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#include "task.h"
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/* Console output macros */
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#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
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/* The size must be a power of 2 */
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#define I2C_MAX_BUFFER_SIZE 0x100
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#define I2C_SIZE_MASK (I2C_MAX_BUFFER_SIZE - 1)
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#define I2C_READ_MAXFIFO_DATA 16
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#define I2C_ENHANCED_CH_INTERVAL 0x80
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/* Store master to slave data of channel D, E, F by DMA */
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static uint8_t in_data[I2C_ENHANCED_PORT_COUNT][I2C_MAX_BUFFER_SIZE]
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__attribute__((section(".h2ram.pool.i2cslv")));
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/* Store slave to master data of channel D, E, F by DMA */
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static uint8_t out_data[I2C_ENHANCED_PORT_COUNT][I2C_MAX_BUFFER_SIZE]
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__attribute__((section(".h2ram.pool.i2cslv")));
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/* Store read and write data of channel A by FIFO mode */
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static uint8_t pbuffer[I2C_MAX_BUFFER_SIZE];
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static uint32_t w_index;
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static uint32_t r_index;
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static int wr_done[I2C_ENHANCED_PORT_COUNT];
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void buffer_index_reset(void)
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{
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/* Reset write buffer index */
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w_index = 0;
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/* Reset read buffer index */
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r_index = 0;
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}
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/* Data structure to define I2C slave control configuration. */
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struct i2c_slv_ctrl_t {
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int irq; /* slave irq */
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/* offset from base 0x00F03500 register; -1 means unused. */
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int offset;
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enum clock_gate_offsets clock_gate;
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int dma_index;
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};
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/* I2C slave control */
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const struct i2c_slv_ctrl_t i2c_slv_ctrl[] = {
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[IT83XX_I2C_CH_A] = {.irq = IT83XX_IRQ_SMB_A, .offset = -1,
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.clock_gate = CGC_OFFSET_SMBA, .dma_index = -1},
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[IT83XX_I2C_CH_D] = {.irq = IT83XX_IRQ_SMB_D, .offset = 0x180,
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.clock_gate = CGC_OFFSET_SMBD, .dma_index = 0},
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[IT83XX_I2C_CH_E] = {.irq = IT83XX_IRQ_SMB_E, .offset = 0x0,
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.clock_gate = CGC_OFFSET_SMBE, .dma_index = 1},
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[IT83XX_I2C_CH_F] = {.irq = IT83XX_IRQ_SMB_F, .offset = 0x80,
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.clock_gate = CGC_OFFSET_SMBF, .dma_index = 2},
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};
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void i2c_slave_read_write_data(int port)
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{
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int slv_status, i;
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/* I2C slave channel A FIFO mode */
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if (port < I2C_STANDARD_PORT_COUNT) {
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int count;
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slv_status = IT83XX_SMB_SLSTA;
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/* bit0-4 : FIFO byte count */
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count = IT83XX_SMB_SFFSTA & 0x1F;
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/* Slave data register is waiting for read or write. */
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if (slv_status & IT83XX_SMB_SDS) {
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/* Master to read data */
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if (slv_status & IT83XX_SMB_RCS) {
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for (i = 0; i < I2C_READ_MAXFIFO_DATA; i++)
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/* Return buffer data to master */
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IT83XX_SMB_SLDA =
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pbuffer[(i + r_index) & I2C_SIZE_MASK];
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/* Index to next 16 bytes of read buffer */
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r_index += I2C_READ_MAXFIFO_DATA;
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}
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/* Master to write data */
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else {
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/* FIFO Full */
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if (IT83XX_SMB_SFFSTA & IT83XX_SMB_SFFFULL) {
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for (i = 0; i < count; i++)
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/* Get data from master to buffer */
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pbuffer[(w_index + i) &
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I2C_SIZE_MASK] = IT83XX_SMB_SLDA;
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}
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/* Index to next byte of write buffer */
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w_index += count;
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}
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}
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/* Stop condition, indicate stop condition detected. */
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if (slv_status & IT83XX_SMB_SPDS) {
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/* Read data less 16 bytes status */
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if (slv_status & IT83XX_SMB_RCS) {
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/* Disable FIFO mode to clear left count */
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IT83XX_SMB_SFFCTL &= ~IT83XX_SMB_SAFE;
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/* Slave A FIFO Enable */
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IT83XX_SMB_SFFCTL |= IT83XX_SMB_SAFE;
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}
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/* Master to write data */
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else {
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for (i = 0; i < count; i++)
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/* Get data from master to buffer */
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pbuffer[(i + w_index) &
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I2C_SIZE_MASK] = IT83XX_SMB_SLDA;
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}
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/* Reset read and write buffer index */
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buffer_index_reset();
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}
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/* Slave time status, timeout status occurs. */
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if (slv_status & IT83XX_SMB_STS) {
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/* Reset read and write buffer index */
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buffer_index_reset();
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}
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/* Write clear the slave status */
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IT83XX_SMB_SLSTA = slv_status;
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}
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/* Enhanced I2C slave channel D, E, F DMA mode */
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else {
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int ch, idx;
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/* Get enhanced i2c channel */
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ch = i2c_slv_ctrl[port].offset / I2C_ENHANCED_CH_INTERVAL;
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idx = i2c_slv_ctrl[port].dma_index;
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/* Interrupt pending */
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if (IT83XX_I2C_STR(ch) & IT83XX_I2C_INTPEND) {
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slv_status = IT83XX_I2C_IRQ_ST(ch);
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/* Master to read data */
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if (slv_status & IT83XX_I2C_IDR_CLR) {
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/*
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* TODO(b:129360157): Return buffer data by
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* "out_data" array.
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* Ex: Write data to buffer from 0x00 to 0xFF
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*/
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for (i = 0; i < I2C_MAX_BUFFER_SIZE; i++)
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out_data[idx][i] = i;
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}
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/* Master to write data */
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if (slv_status & IT83XX_I2C_IDW_CLR) {
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/* Master to write data finish flag */
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wr_done[idx] = 1;
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}
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/* Slave finish */
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if (slv_status & IT83XX_I2C_P_CLR) {
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if (wr_done[idx]) {
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/*
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* TODO(b:129360157): Handle master write
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* data by "in_data" array.
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*/
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CPRINTS("WData: %.*h",
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I2C_MAX_BUFFER_SIZE, in_data[idx]);
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wr_done[idx] = 0;
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}
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}
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/* Write clear the slave status */
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IT83XX_I2C_IRQ_ST(ch) = slv_status;
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}
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/* Hardware reset */
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IT83XX_I2C_CTR(ch) |= IT83XX_I2C_HALT;
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}
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}
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void i2c_slv_interrupt(int port)
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{
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/* Slave to read and write fifo data */
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i2c_slave_read_write_data(port);
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/* Clear the interrupt status */
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task_clear_pending_irq(i2c_slv_ctrl[port].irq);
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}
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void i2c_slave_enable(int port, uint8_t slv_addr)
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{
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clock_enable_peripheral(i2c_slv_ctrl[port].clock_gate, 0, 0);
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/* I2C slave channel A FIFO mode */
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if (port < I2C_STANDARD_PORT_COUNT) {
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/* This field defines the SMCLK0/1/2 clock/data low timeout. */
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IT83XX_SMB_25MS = I2C_CLK_LOW_TIMEOUT;
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/* bit0 : Slave A FIFO Enable */
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IT83XX_SMB_SFFCTL |= IT83XX_SMB_SAFE;
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/*
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* bit1 : Slave interrupt enable.
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* bit2 : SMCLK/SMDAT will be released if timeout.
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* bit3 : Slave detect STOP condition interrupt enable.
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*/
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IT83XX_SMB_SICR = 0x0E;
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/* Slave address 1 */
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IT83XX_SMB_RESLADR = slv_addr;
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/* Write clear all slave status */
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IT83XX_SMB_SLSTA = 0xE7;
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/* bit5 : Enable the SMBus slave device */
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IT83XX_SMB_HOCTL2(port) |= IT83XX_SMB_SLVEN;
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}
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/* Enhanced I2C slave channel D, E, F DMA mode */
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else {
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int ch, idx;
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uint32_t in_data_addr, out_data_addr;
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/* Get enhanced i2c channel */
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ch = i2c_slv_ctrl[port].offset / I2C_ENHANCED_CH_INTERVAL;
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idx = i2c_slv_ctrl[port].dma_index;
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switch (port) {
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case IT83XX_I2C_CH_D:
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/* Enable I2C D channel */
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IT83XX_GPIO_GRC2 |= (1 << 5);
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break;
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case IT83XX_I2C_CH_E:
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/* Enable I2C E channel */
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IT83XX_GCTRL_PMER1 |= (1 << 0);
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break;
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case IT83XX_I2C_CH_F:
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/* Enable I2C F channel */
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IT83XX_GCTRL_PMER1 |= (1 << 1);
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break;
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}
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/* Software reset */
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IT83XX_I2C_DHTR(ch) |= (1 << 7);
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IT83XX_I2C_DHTR(ch) &= ~(1 << 7);
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/* This field defines the SMCLK3/4/5 clock/data low timeout. */
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IT83XX_I2C_TOR(ch) = I2C_CLK_LOW_TIMEOUT;
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/* Bit stretching */
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IT83XX_I2C_TOS(ch) |= IT83XX_I2C_CLK_STR;
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/* Slave address(8-bit)*/
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IT83XX_I2C_IDR(ch) = slv_addr << 1;
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/* I2C interrupt enable and set acknowledge */
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IT83XX_I2C_CTR(ch) = IT83XX_I2C_HALT |
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IT83XX_I2C_INTEN | IT83XX_I2C_ACK;
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/*
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* bit3 : Slave ID write flag
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* bit2 : Slave ID read flag
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* bit1 : Slave received data flag
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* bit0 : Slave finish
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*/
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IT83XX_I2C_IRQ_ST(ch) = 0xFF;
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/* Clear read and write data buffer of DMA */
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memset(in_data[idx], 0, I2C_MAX_BUFFER_SIZE);
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memset(out_data[idx], 0, I2C_MAX_BUFFER_SIZE);
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if (IS_ENABLED(CHIP_ILM_DLM_ORDER)) {
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in_data_addr = (uint32_t)in_data[idx] & 0xffffff;
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out_data_addr = (uint32_t)out_data[idx] & 0xffffff;
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} else {
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in_data_addr = (uint32_t)in_data[idx] & 0xfff;
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out_data_addr = (uint32_t)out_data[idx] & 0xfff;
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}
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/* DMA write target address register */
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IT83XX_I2C_RAMHA(ch) = in_data_addr >> 8;
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IT83XX_I2C_RAMLA(ch) = in_data_addr;
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if (IS_ENABLED(CHIP_ILM_DLM_ORDER)) {
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/*
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* DMA write target address register
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* for high order byte
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*/
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IT83XX_I2C_RAMH2A(ch) = in_data_addr >> 16;
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/*
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* DMA read target address register
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* for high order byte
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*/
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IT83XX_I2C_CMD_ADDH2(ch) = out_data_addr >> 16;
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IT83XX_I2C_CMD_ADDH(ch) = out_data_addr >> 8;
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IT83XX_I2C_CMD_ADDL(ch) = out_data_addr;
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} else {
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/* DMA read target address register */
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IT83XX_I2C_RAMHA2(ch) = out_data_addr >> 8;
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IT83XX_I2C_RAMLA2(ch) = out_data_addr;
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}
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/* I2C module enable and command queue mode */
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IT83XX_I2C_CTR1(ch) = IT83XX_I2C_COMQ_EN |
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IT83XX_I2C_MDL_EN;
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}
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}
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static void i2c_slave_init(void)
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{
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int i, p;
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/* DLM 52k~56k size select enable */
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IT83XX_GCTRL_MCCR2 |= (1 << 4);
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/* Enable I2C Slave function */
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for (i = 0; i < i2c_slvs_used; i++) {
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/* I2c slave port mapping. */
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p = i2c_slv_ports[i].port;
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/* To enable slave ch[x] */
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i2c_slave_enable(p, i2c_slv_ports[i].slave_adr);
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/* Clear the interrupt status */
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task_clear_pending_irq(i2c_slv_ctrl[p].irq);
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/* enable i2c interrupt */
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task_enable_irq(i2c_slv_ctrl[p].irq);
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}
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}
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DECLARE_HOOK(HOOK_INIT, i2c_slave_init, HOOK_PRIO_INIT_I2C + 1);
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