112 lines
3.1 KiB
C
112 lines
3.1 KiB
C
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/* Copyright 2013 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*
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* IT83xx chip-specific part of the IRQ handling.
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*/
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#include "common.h"
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#include "irq_chip.h"
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#include "registers.h"
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#include "util.h"
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#define IRQ_GROUP(n, cpu_ints...) \
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{(uint32_t)&CONCAT2(IT83XX_INTC_ISR, n) - IT83XX_INTC_BASE, \
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(uint32_t)&CONCAT2(IT83XX_INTC_IER, n) - IT83XX_INTC_BASE, \
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##cpu_ints}
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static const struct {
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uint8_t isr_off;
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uint8_t ier_off;
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uint8_t cpu_int[8];
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} irq_groups[23] = {
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IRQ_GROUP(0, {-1, 2, 5, 4, 6, 2, 2, 4}),
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IRQ_GROUP(1, { 7, 6, 6, 5, 2, 2, 2, 8}),
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IRQ_GROUP(2, { 6, 2, 8, 8, 8, 2, 12, 12}),
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IRQ_GROUP(3, { 5, 4, 4, 4, 11, 11, 3, 2}),
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IRQ_GROUP(4, {11, 11, 11, 11, 8, 9, 9, 9}),
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IRQ_GROUP(5, { 2, 2, 2, 2, 2, 2, 2, 2}),
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IRQ_GROUP(6, { 2, 2, 2, 2, 2, 2, 2, 2}),
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IRQ_GROUP(7, {10, 10, 3, -1, 3, 3, 3, 3}),
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IRQ_GROUP(8, { 4, 4, 4, 4, 4, 4, -1, 12}),
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IRQ_GROUP(9, { 2, 2, 2, 2, 2, 2, 2, 2}),
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IRQ_GROUP(10, { 3, 6, 12, 12, 5, 2, 2, 2}),
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IRQ_GROUP(11, { 2, 2, 2, 2, 2, 2, 2, 2}),
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IRQ_GROUP(12, { 2, 2, 2, 2, 2, 2, 2, 2}),
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IRQ_GROUP(13, { 2, 2, 2, 2, 2, 2, 2, 2}),
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IRQ_GROUP(14, { 2, 2, 2, 2, 2, 2, 2, 2}),
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IRQ_GROUP(15, { 2, 2, 2, 2, 2, 2, 2, 2}),
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IRQ_GROUP(16, { 2, 2, 2, 2, 2, 2, 2, -1}),
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IRQ_GROUP(17, { 2, 2, 2, 2, 2, 2, 2, 2}),
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IRQ_GROUP(18, { 2, 2, 2, 2, -1, 4, 4, 7}),
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IRQ_GROUP(19, { 6, 6, 12, 3, 3, 3, 3, 3}),
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IRQ_GROUP(20, {12, 12, 12, 12, 12, 12, 12, -1}),
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#ifdef IT83XX_INTC_GROUP_21_22_SUPPORT
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IRQ_GROUP(21, { 2, 2, 2, 2, 2, 2, 2, 2}),
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IRQ_GROUP(22, { 2, 2, -1, -1, -1, -1, -1, -1}),
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#else
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IRQ_GROUP(21, {-1, -1, -1, -1, -1, -1, -1, -1}),
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IRQ_GROUP(22, {-1, -1, -1, -1, -1, -1, -1, -1}),
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#endif
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};
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int chip_get_intc_group(int irq)
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{
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return irq_groups[irq / 8].cpu_int[irq % 8];
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}
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int chip_enable_irq(int irq)
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{
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int group = irq / 8;
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int bit = irq % 8;
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IT83XX_INTC_REG(irq_groups[group].ier_off) |= BIT(bit);
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if (IS_ENABLED(CHIP_CORE_NDS32))
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IT83XX_INTC_REG(IT83XX_INTC_EXT_IER_OFF(group)) |= BIT(bit);
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return irq_groups[group].cpu_int[bit];
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}
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int chip_disable_irq(int irq)
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{
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int group = irq / 8;
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int bit = irq % 8;
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IT83XX_INTC_REG(irq_groups[group].ier_off) &= ~BIT(bit);
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if (IS_ENABLED(CHIP_CORE_NDS32))
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IT83XX_INTC_REG(IT83XX_INTC_EXT_IER_OFF(group)) &= ~BIT(bit);
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return -1; /* we don't want to mask other IRQs */
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}
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int chip_clear_pending_irq(int irq)
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{
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int group = irq / 8;
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int bit = irq % 8;
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/* always write 1 clear, no | */
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IT83XX_INTC_REG(irq_groups[group].isr_off) = BIT(bit);
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return -1; /* everything has been done */
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}
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int chip_trigger_irq(int irq)
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{
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int group = irq / 8;
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int bit = irq % 8;
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return irq_groups[group].cpu_int[bit];
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}
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void chip_init_irqs(void)
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{
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int i;
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/* Clear all IERx and EXT_IERx */
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for (i = 0; i < ARRAY_SIZE(irq_groups); i++) {
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IT83XX_INTC_REG(irq_groups[i].ier_off) = 0;
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if (IS_ENABLED(CHIP_CORE_NDS32))
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IT83XX_INTC_REG(IT83XX_INTC_EXT_IER_OFF(i)) = 0;
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}
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}
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