384 lines
9.9 KiB
C
384 lines
9.9 KiB
C
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/* Copyright 2012 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* GPIO module for Chrome EC */
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#include "clock.h"
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#include "common.h"
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#include "gpio.h"
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#include "hooks.h"
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#include "registers.h"
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#include "switch.h"
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#include "task.h"
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#include "timer.h"
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#include "util.h"
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/* 0-terminated list of GPIO base addresses */
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static const uint32_t gpio_bases[] = {
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LM4_GPIO_A, LM4_GPIO_B, LM4_GPIO_C, LM4_GPIO_D,
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LM4_GPIO_E, LM4_GPIO_F, LM4_GPIO_G, LM4_GPIO_H,
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LM4_GPIO_J, LM4_GPIO_K, LM4_GPIO_L, LM4_GPIO_M,
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LM4_GPIO_N, LM4_GPIO_P, LM4_GPIO_Q, 0
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};
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/**
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* Find the index of a GPIO port base address
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*
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* This is used by the clock gating registers.
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*
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* @param port_base Base address to find (LM4_GPIO_[A-Q])
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*
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* @return The index, or -1 if no match.
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*/
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static int find_gpio_port_index(uint32_t port_base)
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{
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int i;
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for (i = 0; gpio_bases[i]; i++) {
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if (gpio_bases[i] == port_base)
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return i;
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}
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return -1;
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}
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void gpio_set_alternate_function(uint32_t port, uint32_t mask, int func)
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{
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int port_index = find_gpio_port_index(port);
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int cgmask;
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/* Ignore (do nothing for) invalid port values */
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if (port_index < 0)
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return;
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/* Enable the GPIO port in run and sleep. */
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cgmask = 1 << port_index;
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clock_enable_peripheral(CGC_OFFSET_GPIO, cgmask,
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CGC_MODE_RUN | CGC_MODE_SLEEP);
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if (func >= 0) {
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int pctlmask = 0;
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int i;
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/* Expand mask from bits to nibbles */
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for (i = 0; i < 8; i++) {
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if (mask & BIT(i))
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pctlmask |= 1 << (4 * i);
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}
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LM4_GPIO_PCTL(port) =
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(LM4_GPIO_PCTL(port) & ~(pctlmask * 0xf)) |
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(pctlmask * func);
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LM4_GPIO_AFSEL(port) |= mask;
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} else {
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LM4_GPIO_AFSEL(port) &= ~mask;
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}
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}
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test_mockable int gpio_get_level(enum gpio_signal signal)
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{
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return LM4_GPIO_DATA(gpio_list[signal].port,
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gpio_list[signal].mask) ? 1 : 0;
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}
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void gpio_set_level(enum gpio_signal signal, int value)
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{
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/*
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* Ok to write 0xff because LM4_GPIO_DATA bit-masks only the bit
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* we care about.
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*/
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LM4_GPIO_DATA(gpio_list[signal].port,
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gpio_list[signal].mask) = (value ? 0xff : 0);
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}
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void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
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{
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/*
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* Select open drain first, so that we don't glitch the signal
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* when changing the line to an output.
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*/
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if (flags & GPIO_OPEN_DRAIN)
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LM4_GPIO_ODR(port) |= mask;
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else
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LM4_GPIO_ODR(port) &= ~mask;
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if (flags & GPIO_OUTPUT)
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LM4_GPIO_DIR(port) |= mask;
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else
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LM4_GPIO_DIR(port) &= ~mask;
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/* Handle pullup / pulldown */
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if (flags & GPIO_PULL_UP) {
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LM4_GPIO_PUR(port) |= mask;
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} else if (flags & GPIO_PULL_DOWN) {
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LM4_GPIO_PDR(port) |= mask;
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} else {
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/* No pull up/down */
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LM4_GPIO_PUR(port) &= ~mask;
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LM4_GPIO_PDR(port) &= ~mask;
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}
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/* Set up interrupt type */
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if (flags & (GPIO_INT_F_LOW | GPIO_INT_F_HIGH))
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LM4_GPIO_IS(port) |= mask;
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else
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LM4_GPIO_IS(port) &= ~mask;
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if (flags & (GPIO_INT_F_RISING | GPIO_INT_F_HIGH))
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LM4_GPIO_IEV(port) |= mask;
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else
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LM4_GPIO_IEV(port) &= ~mask;
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/* Handle interrupting on both edges */
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if ((flags & GPIO_INT_F_RISING) &&
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(flags & GPIO_INT_F_FALLING))
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LM4_GPIO_IBE(port) |= mask;
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else
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LM4_GPIO_IBE(port) &= ~mask;
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if (flags & GPIO_ANALOG)
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LM4_GPIO_DEN(port) &= ~mask;
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else
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LM4_GPIO_DEN(port) |= mask;
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/* Set level */
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if (flags & GPIO_HIGH)
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LM4_GPIO_DATA(port, mask) = 0xff;
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else if (flags & GPIO_LOW)
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LM4_GPIO_DATA(port, mask) = 0;
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}
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int gpio_enable_interrupt(enum gpio_signal signal)
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{
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const struct gpio_info *g = gpio_list + signal;
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/* Fail if no interrupt handler */
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if (signal >= GPIO_IH_COUNT)
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return EC_ERROR_UNKNOWN;
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LM4_GPIO_IM(g->port) |= g->mask;
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return EC_SUCCESS;
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}
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int gpio_disable_interrupt(enum gpio_signal signal)
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{
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const struct gpio_info *g = gpio_list + signal;
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/* Fail if no interrupt handler */
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if (signal >= GPIO_IH_COUNT)
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return EC_ERROR_UNKNOWN;
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LM4_GPIO_IM(g->port) &= ~g->mask;
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return EC_SUCCESS;
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}
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int gpio_clear_pending_interrupt(enum gpio_signal signal)
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{
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const struct gpio_info *g = gpio_list + signal;
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/* Fail if no interrupt handler */
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if (signal >= GPIO_IH_COUNT)
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return EC_ERROR_INVAL;
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LM4_GPIO_ICR(g->port) |= g->mask;
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return EC_SUCCESS;
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}
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#ifdef CONFIG_LOW_POWER_IDLE
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/**
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* Convert GPIO port to a mask that can be used to set the
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* clock gate control register for GPIOs.
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*/
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static int gpio_port_to_clock_gate_mask(uint32_t gpio_port)
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{
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int index = find_gpio_port_index(gpio_port);
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return index >= 0 ? BIT(index) : 0;
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}
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#endif
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void gpio_pre_init(void)
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{
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const struct gpio_info *g = gpio_list;
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int is_warm = 0;
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int i;
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if (LM4_SYSTEM_RCGCGPIO == 0x7fff) {
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/* This is a warm reboot */
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is_warm = 1;
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} else {
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/*
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* Enable clocks to all the GPIO blocks since we use all of
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* them as GPIOs in run and sleep modes.
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*/
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clock_enable_peripheral(CGC_OFFSET_GPIO, 0x7fff,
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CGC_MODE_RUN | CGC_MODE_SLEEP);
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}
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/*
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* Disable GPIO commit control for PD7 and PF0, since we don't use the
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* NMI pin function.
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*/
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LM4_GPIO_LOCK(LM4_GPIO_D) = LM4_GPIO_LOCK_UNLOCK;
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LM4_GPIO_CR(LM4_GPIO_D) |= 0x80;
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LM4_GPIO_LOCK(LM4_GPIO_D) = 0;
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LM4_GPIO_LOCK(LM4_GPIO_F) = LM4_GPIO_LOCK_UNLOCK;
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LM4_GPIO_CR(LM4_GPIO_F) |= 0x01;
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LM4_GPIO_LOCK(LM4_GPIO_F) = 0;
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/* Clear SSI0 alternate function on PA2:5 */
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LM4_GPIO_AFSEL(LM4_GPIO_A) &= ~0x3c;
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/* Mask all GPIO interrupts */
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for (i = 0; gpio_bases[i]; i++)
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LM4_GPIO_IM(gpio_bases[i]) = 0;
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/* Set all GPIOs to defaults */
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for (i = 0; i < GPIO_COUNT; i++, g++) {
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int flags = g->flags;
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if (flags & GPIO_DEFAULT)
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continue;
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#ifdef CONFIG_LOW_POWER_IDLE
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/*
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* Enable board specific GPIO ports to interrupt deep sleep by
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* providing a clock to that port in deep sleep mode.
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*/
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if (flags & GPIO_INT_DSLEEP) {
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clock_enable_peripheral(CGC_OFFSET_GPIO,
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gpio_port_to_clock_gate_mask(g->port),
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CGC_MODE_ALL);
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}
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#endif
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/*
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* If this is a warm reboot, don't set the output levels or
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* we'll shut off the main chipset.
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*/
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if (is_warm)
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flags &= ~(GPIO_LOW | GPIO_HIGH);
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/* Set up GPIO based on flags */
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gpio_set_flags_by_mask(g->port, g->mask, flags);
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/* Use as GPIO, not alternate function */
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gpio_set_alternate_function(g->port, g->mask, -1);
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}
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#ifdef CONFIG_LOW_POWER_IDLE
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/*
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* Enable KB scan row to interrupt deep sleep by providing a clock
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* signal to that port in deep sleep mode.
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*/
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clock_enable_peripheral(CGC_OFFSET_GPIO,
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gpio_port_to_clock_gate_mask(KB_SCAN_ROW_GPIO),
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CGC_MODE_ALL);
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#endif
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}
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/* List of GPIO IRQs to enable. Don't automatically enable interrupts for
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* the keyboard input GPIO bank - that's handled separately. Of course the
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* bank is different for different systems. */
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static const uint8_t gpio_irqs[] = {
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LM4_IRQ_GPIOA, LM4_IRQ_GPIOB, LM4_IRQ_GPIOC, LM4_IRQ_GPIOD,
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LM4_IRQ_GPIOE, LM4_IRQ_GPIOF, LM4_IRQ_GPIOG, LM4_IRQ_GPIOH,
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LM4_IRQ_GPIOJ,
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#if defined(KB_SCAN_ROW_IRQ) && (KB_SCAN_ROW_IRQ != LM4_IRQ_GPIOK)
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LM4_IRQ_GPIOK,
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#endif
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LM4_IRQ_GPIOL, LM4_IRQ_GPIOM,
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#if defined(KB_SCAN_ROW_IRQ) && (KB_SCAN_ROW_IRQ != LM4_IRQ_GPION)
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LM4_IRQ_GPION,
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#endif
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LM4_IRQ_GPIOP, LM4_IRQ_GPIOQ
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};
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static void gpio_init(void)
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{
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int i;
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/* Enable IRQs now that pins are set up */
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for (i = 0; i < ARRAY_SIZE(gpio_irqs); i++)
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task_enable_irq(gpio_irqs[i]);
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}
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DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
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/*****************************************************************************/
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/* Interrupt handlers */
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/**
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* Handle a GPIO interrupt.
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*
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* @param port GPIO port (LM4_GPIO_*)
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* @param mis Masked interrupt status value for that port
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*/
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static void gpio_interrupt(int port, uint32_t mis)
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{
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int i = 0;
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const struct gpio_info *g = gpio_list;
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for (i = 0; i < GPIO_IH_COUNT && mis; i++, g++) {
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if (port == g->port && (mis & g->mask)) {
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gpio_irq_handlers[i](i);
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mis &= ~g->mask;
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}
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}
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}
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/**
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* Handlers for each GPIO port. These read and clear the interrupt bits for
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* the port, then call the master handler above.
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*/
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#define GPIO_IRQ_FUNC(irqfunc, gpiobase) \
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void irqfunc(void) \
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{ \
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uint32_t mis = LM4_GPIO_MIS(gpiobase); \
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LM4_GPIO_ICR(gpiobase) = mis; \
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gpio_interrupt(gpiobase, mis); \
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}
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GPIO_IRQ_FUNC(__gpio_a_interrupt, LM4_GPIO_A);
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GPIO_IRQ_FUNC(__gpio_b_interrupt, LM4_GPIO_B);
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GPIO_IRQ_FUNC(__gpio_c_interrupt, LM4_GPIO_C);
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GPIO_IRQ_FUNC(__gpio_d_interrupt, LM4_GPIO_D);
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GPIO_IRQ_FUNC(__gpio_e_interrupt, LM4_GPIO_E);
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GPIO_IRQ_FUNC(__gpio_f_interrupt, LM4_GPIO_F);
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GPIO_IRQ_FUNC(__gpio_g_interrupt, LM4_GPIO_G);
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GPIO_IRQ_FUNC(__gpio_h_interrupt, LM4_GPIO_H);
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GPIO_IRQ_FUNC(__gpio_j_interrupt, LM4_GPIO_J);
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#if defined(KB_SCAN_ROW_GPIO) && (KB_SCAN_ROW_GPIO != LM4_GPIO_K)
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GPIO_IRQ_FUNC(__gpio_k_interrupt, LM4_GPIO_K);
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#endif
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GPIO_IRQ_FUNC(__gpio_l_interrupt, LM4_GPIO_L);
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GPIO_IRQ_FUNC(__gpio_m_interrupt, LM4_GPIO_M);
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#if defined(KB_SCAN_ROW_GPIO) && (KB_SCAN_ROW_GPIO != LM4_GPIO_N)
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GPIO_IRQ_FUNC(__gpio_n_interrupt, LM4_GPIO_N);
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#endif
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GPIO_IRQ_FUNC(__gpio_p_interrupt, LM4_GPIO_P);
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GPIO_IRQ_FUNC(__gpio_q_interrupt, LM4_GPIO_Q);
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#undef GPIO_IRQ_FUNC
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/*
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* Declare IRQs. Nesting this macro inside the GPIO_IRQ_FUNC macro works
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* poorly because DECLARE_IRQ() stringizes its inputs.
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||
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*/
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DECLARE_IRQ(LM4_IRQ_GPIOA, __gpio_a_interrupt, 1);
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DECLARE_IRQ(LM4_IRQ_GPIOB, __gpio_b_interrupt, 1);
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DECLARE_IRQ(LM4_IRQ_GPIOC, __gpio_c_interrupt, 1);
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DECLARE_IRQ(LM4_IRQ_GPIOD, __gpio_d_interrupt, 1);
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DECLARE_IRQ(LM4_IRQ_GPIOE, __gpio_e_interrupt, 1);
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DECLARE_IRQ(LM4_IRQ_GPIOF, __gpio_f_interrupt, 1);
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DECLARE_IRQ(LM4_IRQ_GPIOG, __gpio_g_interrupt, 1);
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DECLARE_IRQ(LM4_IRQ_GPIOH, __gpio_h_interrupt, 1);
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DECLARE_IRQ(LM4_IRQ_GPIOJ, __gpio_j_interrupt, 1);
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#if defined(KB_SCAN_ROW_GPIO) && (KB_SCAN_ROW_GPIO != LM4_GPIO_K)
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DECLARE_IRQ(LM4_IRQ_GPIOK, __gpio_k_interrupt, 1);
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#endif
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DECLARE_IRQ(LM4_IRQ_GPIOL, __gpio_l_interrupt, 1);
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DECLARE_IRQ(LM4_IRQ_GPIOM, __gpio_m_interrupt, 1);
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||
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#if defined(KB_SCAN_ROW_GPIO) && (KB_SCAN_ROW_GPIO != LM4_GPIO_N)
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DECLARE_IRQ(LM4_IRQ_GPION, __gpio_n_interrupt, 1);
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#endif
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DECLARE_IRQ(LM4_IRQ_GPIOP, __gpio_p_interrupt, 1);
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DECLARE_IRQ(LM4_IRQ_GPIOQ, __gpio_q_interrupt, 1);
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