413 lines
10 KiB
C
413 lines
10 KiB
C
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/* Copyright 2013 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* I2C port module for Chrome EC */
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#include "atomic.h"
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#include "clock.h"
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#include "common.h"
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#include "console.h"
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#include "gpio.h"
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#include "hooks.h"
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#include "i2c.h"
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#include "registers.h"
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#include "task.h"
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#include "timer.h"
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#include "util.h"
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#define CPUTS(outstr) cputs(CC_I2C, outstr)
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#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
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/* Flags for writes to MCS */
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#define LM4_I2C_MCS_RUN BIT(0)
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#define LM4_I2C_MCS_START BIT(1)
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#define LM4_I2C_MCS_STOP BIT(2)
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#define LM4_I2C_MCS_ACK BIT(3)
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#define LM4_I2C_MCS_HS BIT(4)
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#define LM4_I2C_MCS_QCMD BIT(5)
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/* Flags for reads from MCS */
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#define LM4_I2C_MCS_BUSY BIT(0)
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#define LM4_I2C_MCS_ERROR BIT(1)
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#define LM4_I2C_MCS_ADRACK BIT(2)
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#define LM4_I2C_MCS_DATACK BIT(3)
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#define LM4_I2C_MCS_ARBLST BIT(4)
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#define LM4_I2C_MCS_IDLE BIT(5)
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#define LM4_I2C_MCS_BUSBSY BIT(6)
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#define LM4_I2C_MCS_CLKTO BIT(7)
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/*
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* Minimum delay between resetting the port or sending a stop condition, and
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* when the port can be expected to be back in an idle state (and the slave
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* has had long enough to see the start/stop condition edges).
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*
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* 500 us = 50 clocks at 100 KHz bus speed. This has been experimentally
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* determined to be enough.
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*/
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#define I2C_IDLE_US 500
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/* IRQ for each port */
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static const uint32_t i2c_irqs[] = {LM4_IRQ_I2C0, LM4_IRQ_I2C1, LM4_IRQ_I2C2,
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LM4_IRQ_I2C3, LM4_IRQ_I2C4, LM4_IRQ_I2C5};
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BUILD_ASSERT(ARRAY_SIZE(i2c_irqs) == I2C_PORT_COUNT);
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/* I2C port state data */
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struct i2c_port_data {
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const uint8_t *out; /* Output data pointer */
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int out_size; /* Output data to transfer, in bytes */
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uint8_t *in; /* Input data pointer */
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int in_size; /* Input data to transfer, in bytes */
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int flags; /* Flags (I2C_XFER_*) */
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int idx; /* Index into input/output data */
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int err; /* Error code, if any */
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uint32_t timeout_us; /* Transaction timeout, or 0 to use default */
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/* Task waiting on port, or TASK_ID_INVALID if none. */
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volatile int task_waiting;
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};
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static struct i2c_port_data pdata[I2C_PORT_COUNT];
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int i2c_is_busy(int port)
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{
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return LM4_I2C_MCS(port) & LM4_I2C_MCS_BUSBSY;
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}
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/**
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* I2C transfer engine.
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*
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* @return Zero when done with transfer (ready to wake task).
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*
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* MCS sequence on multi-byte write:
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* 0x3 0x1 0x1 ... 0x1 0x5
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* Single byte write:
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* 0x7
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*
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* MCS receive sequence on multi-byte read:
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* 0xb 0x9 0x9 ... 0x9 0x5
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* Single byte read:
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* 0x7
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*/
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int i2c_do_work(int port)
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{
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struct i2c_port_data *pd = pdata + port;
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uint32_t reg_mcs = LM4_I2C_MCS_RUN;
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if (pd->flags & I2C_XFER_START) {
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/* Set start bit on first byte */
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reg_mcs |= LM4_I2C_MCS_START;
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pd->flags &= ~I2C_XFER_START;
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} else if (LM4_I2C_MCS(port) & (LM4_I2C_MCS_CLKTO | LM4_I2C_MCS_ARBLST |
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LM4_I2C_MCS_ERROR)) {
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/*
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* Error after starting; abort transfer. Ignore errors at
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* start because arbitration and timeout errors are taken care
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* of in chip_i2c_xfer(), and slave ack failures will
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* automatically clear once we send a start condition.
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*/
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pd->err = EC_ERROR_UNKNOWN;
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return 0;
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}
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if (pd->out_size) {
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/* Send next byte of output */
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LM4_I2C_MDR(port) = *(pd->out++);
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pd->idx++;
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/* Handle starting to send last byte */
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if (pd->idx == pd->out_size) {
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/* Done with output after this */
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pd->out_size = 0;
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pd->idx = 0;
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/* Resend start bit when changing direction */
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pd->flags |= I2C_XFER_START;
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/*
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* Send stop bit after last byte if the stop flag is
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* on, and caller doesn't expect to receive data.
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*/
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if ((pd->flags & I2C_XFER_STOP) && pd->in_size == 0)
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reg_mcs |= LM4_I2C_MCS_STOP;
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}
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LM4_I2C_MCS(port) = reg_mcs;
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return 1;
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} else if (pd->in_size) {
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if (pd->idx) {
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/* Copy the byte we just read */
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*(pd->in++) = LM4_I2C_MDR(port) & 0xff;
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} else {
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/* Starting receive; switch to receive address */
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LM4_I2C_MSA(port) |= 0x01;
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}
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if (pd->idx < pd->in_size) {
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/* More data to read */
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pd->idx++;
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/* ACK all bytes except the last one */
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if ((pd->flags & I2C_XFER_STOP) &&
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pd->idx == pd->in_size)
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reg_mcs |= LM4_I2C_MCS_STOP;
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else
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reg_mcs |= LM4_I2C_MCS_ACK;
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LM4_I2C_MCS(port) = reg_mcs;
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return 1;
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}
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}
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/* If we're still here, done with transfer */
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return 0;
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}
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int chip_i2c_xfer(const int port, const uint16_t slave_addr_flags,
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const uint8_t *out, int out_size,
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uint8_t *in, int in_size, int flags)
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{
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struct i2c_port_data *pd = pdata + port;
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uint32_t reg_mcs = LM4_I2C_MCS(port);
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int events = 0;
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if (out_size == 0 && in_size == 0)
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return EC_SUCCESS;
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/* Copy data to port struct */
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pd->out = out;
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pd->out_size = out_size;
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pd->in = in;
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pd->in_size = in_size;
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pd->flags = flags;
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pd->idx = 0;
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pd->err = 0;
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/* Make sure we're in a good state to start */
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if ((flags & I2C_XFER_START) &&
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((reg_mcs & (LM4_I2C_MCS_CLKTO | LM4_I2C_MCS_ARBLST)) ||
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(i2c_get_line_levels(port) != I2C_LINE_IDLE))) {
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uint32_t tpr = LM4_I2C_MTPR(port);
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CPRINTS("I2C%d Addr:%02X bad status 0x%02x, SCL=%d, SDA=%d",
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port,
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I2C_GET_ADDR(slave_addr_flags),
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reg_mcs,
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i2c_get_line_levels(port) & I2C_LINE_SCL_HIGH,
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i2c_get_line_levels(port) & I2C_LINE_SDA_HIGH);
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/* Attempt to unwedge the port. */
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i2c_unwedge(port);
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/* Clock timeout or arbitration lost. Reset port to clear. */
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atomic_or(LM4_SYSTEM_SRI2C_ADDR, BIT(port));
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clock_wait_cycles(3);
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atomic_clear(LM4_SYSTEM_SRI2C_ADDR, BIT(port));
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clock_wait_cycles(3);
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/* Restore settings */
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LM4_I2C_MCR(port) = 0x10;
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LM4_I2C_MTPR(port) = tpr;
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/*
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* We don't know what edges the slave saw, so sleep long enough
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* that the slave will see the new start condition below.
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*/
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usleep(I2C_IDLE_US);
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}
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/* Set slave address for transmit */
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LM4_I2C_MSA(port) = (I2C_GET_ADDR(slave_addr_flags) << 1) & 0xff;
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/* Enable interrupts */
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pd->task_waiting = task_get_current();
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LM4_I2C_MICR(port) = 0x03;
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LM4_I2C_MIMR(port) = 0x03;
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/* Kick the port interrupt handler to start the transfer */
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task_trigger_irq(i2c_irqs[port]);
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/* Wait for transfer complete or timeout */
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events = task_wait_event_mask(TASK_EVENT_I2C_IDLE, pd->timeout_us);
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/* Disable interrupts */
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LM4_I2C_MIMR(port) = 0x00;
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pd->task_waiting = TASK_ID_INVALID;
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/* Handle timeout */
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if (events & TASK_EVENT_TIMER)
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pd->err = EC_ERROR_TIMEOUT;
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if (pd->err) {
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/* Force port back idle */
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LM4_I2C_MCS(port) = LM4_I2C_MCS_STOP;
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usleep(I2C_IDLE_US);
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}
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return pd->err;
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}
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int i2c_raw_get_scl(int port)
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{
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enum gpio_signal g;
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int ret;
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/* If no SCL pin defined for this port, then return 1 to appear idle. */
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if (get_scl_from_i2c_port(port, &g) != EC_SUCCESS)
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return 1;
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/* If we are driving the pin low, it must be low. */
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if (gpio_get_level(g) == 0)
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return 0;
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/*
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* Otherwise, we need to toggle it to an input to read the true pin
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* state.
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*/
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gpio_set_flags(g, GPIO_INPUT);
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ret = gpio_get_level(g);
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gpio_set_flags(g, GPIO_ODR_HIGH);
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return ret;
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}
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int i2c_raw_get_sda(int port)
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{
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enum gpio_signal g;
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int ret;
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/* If no SDA pin defined for this port, then return 1 to appear idle. */
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if (get_sda_from_i2c_port(port, &g) != EC_SUCCESS)
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return 1;
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/* If we are driving the pin low, it must be low. */
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if (gpio_get_level(g) == 0)
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return 0;
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/*
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* Otherwise, we need to toggle it to an input to read the true pin
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* state.
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*/
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gpio_set_flags(g, GPIO_INPUT);
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ret = gpio_get_level(g);
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gpio_set_flags(g, GPIO_ODR_HIGH);
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return ret;
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}
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int i2c_get_line_levels(int port)
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{
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/* Conveniently, MBMON bit BIT(1) is SDA and BIT(0) is SCL. */
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return LM4_I2C_MBMON(port) & 0x03;
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}
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void i2c_set_timeout(int port, uint32_t timeout)
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{
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pdata[port].timeout_us = timeout ? timeout : I2C_TIMEOUT_DEFAULT_US;
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}
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/*****************************************************************************/
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/* Hooks */
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static void i2c_freq_changed(void)
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{
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int freq = clock_get_freq();
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int i;
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for (i = 0; i < i2c_ports_used; i++) {
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/*
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* From datasheet:
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* SCL_PRD = 2 * (1 + TPR) * (SCL_LP + SCL_HP) * CLK_PRD
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*
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* so:
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* TPR = SCL_PRD / (2 * (SCL_LP + SCL_HP) * CLK_PRD) - 1
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*
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* converting from period to frequency:
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* TPR = CLK_FREQ / (SCL_FREQ * 2 * (SCL_LP + SCL_HP)) - 1
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*/
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const int d = 2 * (6 + 4) * (i2c_ports[i].kbps * 1000);
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/* Round TPR up, so desired kbps is an upper bound */
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const int tpr = (freq + d - 1) / d - 1;
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#ifdef PRINT_I2C_SPEEDS
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const int f = freq / (2 * (1 + tpr) * (6 + 4));
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CPRINTS("I2C%d clk=%d tpr=%d freq=%d",
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i2c_ports[i].port, freq, tpr, f);
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#endif
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LM4_I2C_MTPR(i2c_ports[i].port) = tpr;
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}
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}
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DECLARE_HOOK(HOOK_FREQ_CHANGE, i2c_freq_changed, HOOK_PRIO_DEFAULT);
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static void i2c_init(void)
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{
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uint32_t mask = 0;
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int i;
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/* Enable I2C modules in run and sleep modes. */
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for (i = 0; i < i2c_ports_used; i++)
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mask |= 1 << i2c_ports[i].port;
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clock_enable_peripheral(CGC_OFFSET_I2C, mask,
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CGC_MODE_RUN | CGC_MODE_SLEEP);
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|
|
||
|
|
/* Configure GPIOs */
|
||
|
|
gpio_config_module(MODULE_I2C, 1);
|
||
|
|
|
||
|
|
/* Initialize ports as master, with interrupts enabled */
|
||
|
|
for (i = 0; i < i2c_ports_used; i++)
|
||
|
|
LM4_I2C_MCR(i2c_ports[i].port) = 0x10;
|
||
|
|
|
||
|
|
/* Set initial clock frequency */
|
||
|
|
i2c_freq_changed();
|
||
|
|
|
||
|
|
/* Enable IRQs; no tasks are waiting on ports */
|
||
|
|
for (i = 0; i < I2C_PORT_COUNT; i++) {
|
||
|
|
pdata[i].task_waiting = TASK_ID_INVALID;
|
||
|
|
task_enable_irq(i2c_irqs[i]);
|
||
|
|
|
||
|
|
/* Use default timeout */
|
||
|
|
i2c_set_timeout(i, 0);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
DECLARE_HOOK(HOOK_INIT, i2c_init, HOOK_PRIO_INIT_I2C);
|
||
|
|
|
||
|
|
/**
|
||
|
|
* Handle an interrupt on the specified port.
|
||
|
|
*
|
||
|
|
* @param port I2C port generating interrupt
|
||
|
|
*/
|
||
|
|
static void handle_interrupt(int port)
|
||
|
|
{
|
||
|
|
int id = pdata[port].task_waiting;
|
||
|
|
|
||
|
|
/* Clear the interrupt status */
|
||
|
|
LM4_I2C_MICR(port) = LM4_I2C_MMIS(port);
|
||
|
|
|
||
|
|
/* If no task is waiting, just return */
|
||
|
|
if (id == TASK_ID_INVALID)
|
||
|
|
return;
|
||
|
|
|
||
|
|
/* If done doing work, wake up the task waiting for the transfer */
|
||
|
|
if (!i2c_do_work(port))
|
||
|
|
task_set_event(id, TASK_EVENT_I2C_IDLE, 0);
|
||
|
|
}
|
||
|
|
|
||
|
|
void i2c0_interrupt(void) { handle_interrupt(0); }
|
||
|
|
void i2c1_interrupt(void) { handle_interrupt(1); }
|
||
|
|
void i2c2_interrupt(void) { handle_interrupt(2); }
|
||
|
|
void i2c3_interrupt(void) { handle_interrupt(3); }
|
||
|
|
void i2c4_interrupt(void) { handle_interrupt(4); }
|
||
|
|
void i2c5_interrupt(void) { handle_interrupt(5); }
|
||
|
|
|
||
|
|
DECLARE_IRQ(LM4_IRQ_I2C0, i2c0_interrupt, 2);
|
||
|
|
DECLARE_IRQ(LM4_IRQ_I2C1, i2c1_interrupt, 2);
|
||
|
|
DECLARE_IRQ(LM4_IRQ_I2C2, i2c2_interrupt, 2);
|
||
|
|
DECLARE_IRQ(LM4_IRQ_I2C3, i2c3_interrupt, 2);
|
||
|
|
DECLARE_IRQ(LM4_IRQ_I2C4, i2c4_interrupt, 2);
|
||
|
|
DECLARE_IRQ(LM4_IRQ_I2C5, i2c5_interrupt, 2);
|