485 lines
12 KiB
C
485 lines
12 KiB
C
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/* Copyright 2013 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* Clocks and power management settings */
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#include "clock.h"
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#include "common.h"
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#include "console.h"
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#include "cpu.h"
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#include "hooks.h"
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#include "hwtimer.h"
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#include "pwm.h"
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#include "pwm_chip.h"
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#include "registers.h"
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#include "shared_mem.h"
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#include "system.h"
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#include "task.h"
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#include "timer.h"
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#include "uart.h"
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#include "util.h"
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#include "vboot_hash.h"
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/* Console output macros */
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#define CPUTS(outstr) cputs(CC_CLOCK, outstr)
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#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
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#ifdef CONFIG_LOW_POWER_IDLE
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/* Recovery time for HvySlp2 is 0 usec */
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#define HEAVY_SLEEP_RECOVER_TIME_USEC 75
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#define SET_HTIMER_DELAY_USEC 200
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static int idle_sleep_cnt;
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static int idle_dsleep_cnt;
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static uint64_t total_idle_dsleep_time_us;
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/*
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* Fixed amount of time to keep the console in use flag true after boot in
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* order to give a permanent window in which the heavy sleep mode is not used.
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*/
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#define CONSOLE_IN_USE_ON_BOOT_TIME (15*SECOND)
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static int console_in_use_timeout_sec = 60;
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static timestamp_t console_expire_time;
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#endif /*CONFIG_LOW_POWER_IDLE */
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static int freq = 48000000;
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void clock_wait_cycles(uint32_t cycles)
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{
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asm volatile("1: subs %0, #1\n"
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" bne 1b\n" : "+r"(cycles));
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}
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int clock_get_freq(void)
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{
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return freq;
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}
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void clock_init(void)
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{
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#ifdef CONFIG_CLOCK_CRYSTAL
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/* XOSEL: 0 = Parallel resonant crystal */
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MEC1322_VBAT_CE &= ~0x1;
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#else
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/* XOSEL: 1 = Single ended clock source */
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MEC1322_VBAT_CE |= 0x1;
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#endif
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/* 32K clock enable */
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MEC1322_VBAT_CE |= 0x2;
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#ifdef CONFIG_CLOCK_CRYSTAL
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/* Wait for crystal to stabilize (OSC_LOCK == 1) */
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while (!(MEC1322_PCR_CHIP_OSC_ID & 0x100))
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;
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#endif
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}
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/**
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* Speed through boot + vboot hash calculation, dropping our processor clock
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* only after vboot hashing is completed.
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*/
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static void clock_turbo_disable(void);
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DECLARE_DEFERRED(clock_turbo_disable);
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static void clock_turbo_disable(void)
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{
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#ifdef CONFIG_VBOOT_HASH
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if (vboot_hash_in_progress())
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hook_call_deferred(&clock_turbo_disable_data, 100 * MSEC);
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else
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#endif
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/* Use 12 MHz processor clock for power savings */
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MEC1322_PCR_PROC_CLK_CTL = 4;
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}
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DECLARE_HOOK(HOOK_INIT, clock_turbo_disable, HOOK_PRIO_INIT_VBOOT_HASH + 1);
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#ifdef CONFIG_LOW_POWER_IDLE
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/**
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* initialization of Hibernation timer
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*/
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static void htimer_init(void)
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{
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MEC1322_INT_BLK_EN |= BIT(17);
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MEC1322_INT_ENABLE(17) |= BIT(20); /* GIRQ=17, aggregator bit = 20 */
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MEC1322_HTIMER_PRELOAD = 0; /* disable at beginning */
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task_enable_irq(MEC1322_IRQ_HTIMER);
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}
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/**
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* Use hibernate module to set up an htimer interrupt at a given
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* time from now
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*
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* @param seconds Number of seconds before htimer interrupt
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* @param microseconds Number of microseconds before htimer interrupt
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*/
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static void system_set_htimer_alarm(uint32_t seconds, uint32_t microseconds)
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{
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if (seconds || microseconds) {
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if (seconds > 2) {
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/* count from 2 sec to 2 hrs, mec1322 sec 18.10.2 */
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ASSERT(seconds <= 0xffff / 8);
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MEC1322_HTIMER_CONTROL = 1; /* 0.125(=1/8) per clock */
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/* (number of counts to be loaded)
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* = seconds * ( 8 clocks per second )
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* + microseconds / 125000
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* ---> (0 if (microseconds < 125000)
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*/
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MEC1322_HTIMER_PRELOAD =
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(seconds * 8 + microseconds / 125000);
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} else { /* count up to 2 sec. */
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MEC1322_HTIMER_CONTROL = 0; /* 30.5(= 2/61) usec */
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/* (number of counts to be loaded)
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* = (total microseconds) / 30.5;
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*/
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MEC1322_HTIMER_PRELOAD =
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(seconds * 1000000 + microseconds) * 2 / 61;
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}
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}
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}
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/**
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* return time slept in micro-seconds
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*/
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static timestamp_t system_get_htimer(void)
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{
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uint16_t count;
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timestamp_t time;
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count = MEC1322_HTIMER_COUNT;
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if (MEC1322_HTIMER_CONTROL == 1) /* if > 2 sec */
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/* 0.125 sec per count */
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time.le.lo = (uint32_t)(count * 125000);
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else /* if < 2 sec */
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/* 30.5(=61/2)usec per count */
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time.le.lo = (uint32_t)(count * 61 / 2);
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time.le.hi = 0;
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return time; /* in uSec */
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}
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/**
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* Disable and clear hibernation timer interrupt
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*/
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static void system_reset_htimer_alarm(void)
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{
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MEC1322_HTIMER_PRELOAD = 0;
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}
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/**
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* This is mec1322 specific and equivalent to ARM Cortex's
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* 'DeepSleep' via system control block register, CPU_SCB_SYSCTRL
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*/
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static void prepare_for_deep_sleep(void)
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{
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uint32_t ec_slp_en = MEC1322_PCR_EC_SLP_EN |
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MEC1322_PCR_EC_SLP_EN_SLEEP;
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/* sysTick timer */
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CPU_NVIC_ST_CTRL &= ~ST_ENABLE;
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CPU_NVIC_ST_CTRL &= ~ST_COUNTFLAG;
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/* Disable JTAG */
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MEC1322_EC_JTAG_EN &= ~1;
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/* Power down ADC VREF, ADC_VREF overrides ADC_CTRL. */
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MEC1322_EC_ADC_VREF_PD |= 1;
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/* Stop watchdog */
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MEC1322_WDG_CTL &= ~1;
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/* Stop timers */
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MEC1322_TMR32_CTL(0) &= ~1;
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MEC1322_TMR32_CTL(1) &= ~1;
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MEC1322_TMR16_CTL(0) &= ~1;
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MEC1322_PCR_CHIP_SLP_EN |= 0x3;
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#ifdef CONFIG_PWM
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if (pwm_get_keep_awake_mask())
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ec_slp_en &= ~pwm_get_keep_awake_mask();
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else
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#endif
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/* Disable 100 Khz clock */
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MEC1322_PCR_SLOW_CLK_CTL &= 0xFFFFFC00;
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MEC1322_PCR_EC_SLP_EN = ec_slp_en;
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MEC1322_PCR_HOST_SLP_EN |= MEC1322_PCR_HOST_SLP_EN_SLEEP;
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MEC1322_PCR_EC_SLP_EN2 |= MEC1322_PCR_EC_SLP_EN2_SLEEP;
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#ifndef CONFIG_POWER_S0IX
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MEC1322_LPC_ACT = 0x0;
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#endif
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MEC1322_PCR_SYS_SLP_CTL = 0x2; /* heavysleep 2 */
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CPU_NVIC_ST_CTRL &= ~ST_TICKINT; /* SYS_TICK_INT_DISABLE */
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}
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static void resume_from_deep_sleep(void)
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{
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CPU_NVIC_ST_CTRL |= ST_TICKINT; /* SYS_TICK_INT_ENABLE */
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CPU_NVIC_ST_CTRL |= ST_ENABLE;
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MEC1322_EC_JTAG_EN = 1;
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MEC1322_EC_ADC_VREF_PD &= ~1;
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/* ADC_VREF_PD overrides ADC_CTRL ! */
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/* Enable timer */
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MEC1322_TMR32_CTL(0) |= 1;
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MEC1322_TMR32_CTL(1) |= 1;
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MEC1322_TMR16_CTL(0) |= 1;
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/* Enable watchdog */
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MEC1322_WDG_CTL |= 1;
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MEC1322_PCR_SLOW_CLK_CTL |= 0x1e0;
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MEC1322_PCR_CHIP_SLP_EN &= ~0x3;
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MEC1322_PCR_EC_SLP_EN &= MEC1322_PCR_EC_SLP_EN_WAKE;
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MEC1322_PCR_HOST_SLP_EN &= MEC1322_PCR_HOST_SLP_EN_WAKE;
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MEC1322_PCR_EC_SLP_EN2 &= MEC1322_PCR_EC_SLP_EN2_WAKE;
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MEC1322_PCR_SYS_SLP_CTL = 0xF8; /* default */
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#ifndef CONFIG_POWER_S0IX
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/* Enable LPC */
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MEC1322_LPC_ACT |= 1;
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#endif
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}
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void clock_refresh_console_in_use(void)
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{
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disable_sleep(SLEEP_MASK_CONSOLE);
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/* Set console in use expire time. */
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console_expire_time = get_time();
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console_expire_time.val += console_in_use_timeout_sec * SECOND;
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}
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/**
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* Low power idle task. Executed when no tasks are ready to be scheduled.
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*/
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void __idle(void)
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{
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timestamp_t t0;
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timestamp_t t1;
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timestamp_t ht_t1;
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uint32_t next_delay;
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uint32_t max_sleep_time;
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int time_for_dsleep;
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int uart_ready_for_deepsleep;
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htimer_init(); /* hibernation timer initialize */
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disable_sleep(SLEEP_MASK_CONSOLE);
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console_expire_time.val = get_time().val + CONSOLE_IN_USE_ON_BOOT_TIME;
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/*
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* Print when the idle task starts. This is the lowest priority task,
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* so this only starts once all other tasks have gotten a chance to do
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* their task inits and have gone to sleep.
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*/
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CPRINTS("low power idle task started");
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while (1) {
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/* Disable interrupts */
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interrupt_disable();
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t0 = get_time(); /* uSec */
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/* __hw_clock_event_get() is next programmed timer event */
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next_delay = __hw_clock_event_get() - t0.le.lo;
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time_for_dsleep = next_delay > (HEAVY_SLEEP_RECOVER_TIME_USEC +
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SET_HTIMER_DELAY_USEC);
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max_sleep_time = next_delay - HEAVY_SLEEP_RECOVER_TIME_USEC;
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/* check if there enough time for deep sleep */
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if (DEEP_SLEEP_ALLOWED && time_for_dsleep) {
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/*
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* Check if the console use has expired and console
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* sleep is masked by GPIO(UART-RX) interrupt.
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*/
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if ((sleep_mask & SLEEP_MASK_CONSOLE) &&
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t0.val > console_expire_time.val) {
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/* allow console to sleep. */
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enable_sleep(SLEEP_MASK_CONSOLE);
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/*
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* Wait one clock before checking if heavy sleep
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* is allowed to give time for sleep mask
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* to be updated.
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*/
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clock_wait_cycles(1);
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if (LOW_SPEED_DEEP_SLEEP_ALLOWED)
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CPRINTS("Disable console in deepsleep");
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}
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/* UART is not being used */
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uart_ready_for_deepsleep = LOW_SPEED_DEEP_SLEEP_ALLOWED
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&& !uart_tx_in_progress()
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&& uart_buffer_empty();
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/*
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* Since MEC1322's heavysleep modes requires all block
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* to be sleepable, UART/console's readiness is final
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* decision factor of heavysleep of EC.
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*/
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if (uart_ready_for_deepsleep) {
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idle_dsleep_cnt++;
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/*
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* config UART Rx as GPIO wakeup interrupt
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* source
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*/
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uart_enter_dsleep();
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/* MEC1322 specific deep-sleep mode */
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prepare_for_deep_sleep();
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/*
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* 'max_sleep_time' value should be big
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* enough so that hibernation timer's interrupt
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* triggers only after 'wfi' completes its
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* excution.
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*/
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max_sleep_time -= (get_time().le.lo - t0.le.lo);
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/* setup/enable htimer wakeup interrupt */
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system_set_htimer_alarm(0, max_sleep_time);
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} else {
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idle_sleep_cnt++;
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}
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/* Wait for interrupt: goes into deep sleep. */
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asm("wfi");
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if (uart_ready_for_deepsleep) {
|
||
|
|
|
||
|
|
resume_from_deep_sleep();
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Fast forward timer according to htimer
|
||
|
|
* counter:
|
||
|
|
* Since all blocks including timers will be in
|
||
|
|
* sleep mode, timers stops except hibernate
|
||
|
|
* timer.
|
||
|
|
* And system schedule timer should be corrected
|
||
|
|
* after wakeup by either hibernate timer or
|
||
|
|
* GPIO_UART_RX interrupt.
|
||
|
|
*/
|
||
|
|
ht_t1 = system_get_htimer();
|
||
|
|
|
||
|
|
/* disable/clear htimer wakeup interrupt */
|
||
|
|
system_reset_htimer_alarm();
|
||
|
|
|
||
|
|
t1.val = t0.val +
|
||
|
|
(uint64_t)(max_sleep_time - ht_t1.le.lo);
|
||
|
|
|
||
|
|
force_time(t1);
|
||
|
|
|
||
|
|
/* re-eanble UART */
|
||
|
|
uart_exit_dsleep();
|
||
|
|
|
||
|
|
/* Record time spent in deep sleep. */
|
||
|
|
total_idle_dsleep_time_us +=
|
||
|
|
(uint64_t)(max_sleep_time - ht_t1.le.lo);
|
||
|
|
}
|
||
|
|
|
||
|
|
} else { /* CPU 'Sleep' mode */
|
||
|
|
|
||
|
|
idle_sleep_cnt++;
|
||
|
|
|
||
|
|
asm("wfi");
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
interrupt_enable();
|
||
|
|
} /* while(1) */
|
||
|
|
}
|
||
|
|
|
||
|
|
#ifdef CONFIG_CMD_IDLE_STATS
|
||
|
|
/**
|
||
|
|
* Print low power idle statistics
|
||
|
|
*/
|
||
|
|
static int command_idle_stats(int argc, char **argv)
|
||
|
|
{
|
||
|
|
timestamp_t ts = get_time();
|
||
|
|
|
||
|
|
ccprintf("Num idle calls that sleep: %d\n", idle_sleep_cnt);
|
||
|
|
ccprintf("Num idle calls that deep-sleep: %d\n", idle_dsleep_cnt);
|
||
|
|
|
||
|
|
ccprintf("Total Time spent in deep-sleep(sec): %.6ld(s)\n",
|
||
|
|
total_idle_dsleep_time_us);
|
||
|
|
ccprintf("Total time on: %.6lds\n\n", ts.val);
|
||
|
|
return EC_SUCCESS;
|
||
|
|
}
|
||
|
|
DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats,
|
||
|
|
"",
|
||
|
|
"Print last idle stats");
|
||
|
|
#endif /* defined(CONFIG_CMD_IDLE_STATS) */
|
||
|
|
|
||
|
|
/**
|
||
|
|
* Configure deep sleep clock settings.
|
||
|
|
*/
|
||
|
|
static int command_dsleep(int argc, char **argv)
|
||
|
|
{
|
||
|
|
int v;
|
||
|
|
|
||
|
|
if (argc > 1) {
|
||
|
|
if (parse_bool(argv[1], &v)) {
|
||
|
|
/*
|
||
|
|
* Force deep sleep not to use heavy sleep mode or
|
||
|
|
* allow it to use the heavy sleep mode.
|
||
|
|
*/
|
||
|
|
if (v) /* 'on' */
|
||
|
|
disable_sleep(SLEEP_MASK_FORCE_NO_LOW_SPEED);
|
||
|
|
else /* 'off' */
|
||
|
|
enable_sleep(SLEEP_MASK_FORCE_NO_LOW_SPEED);
|
||
|
|
} else {
|
||
|
|
/* Set console in use timeout. */
|
||
|
|
char *e;
|
||
|
|
v = strtoi(argv[1], &e, 10);
|
||
|
|
if (*e)
|
||
|
|
return EC_ERROR_PARAM1;
|
||
|
|
|
||
|
|
console_in_use_timeout_sec = v;
|
||
|
|
|
||
|
|
/* Refresh console in use to use new timeout. */
|
||
|
|
clock_refresh_console_in_use();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
ccprintf("Sleep mask: %08x\n", sleep_mask);
|
||
|
|
ccprintf("Console in use timeout: %d sec\n",
|
||
|
|
console_in_use_timeout_sec);
|
||
|
|
|
||
|
|
return EC_SUCCESS;
|
||
|
|
}
|
||
|
|
DECLARE_CONSOLE_COMMAND(dsleep, command_dsleep,
|
||
|
|
"[ on | off | <timeout> sec]",
|
||
|
|
"Deep sleep clock settings:\nUse 'on' to force deep "
|
||
|
|
"sleep NOT to enter heavysleep mode.\nUse 'off' to "
|
||
|
|
"allow deep sleep to use heavysleep whenever conditions"
|
||
|
|
"allow.\n"
|
||
|
|
"Give a timeout value for the console in use timeout.\n"
|
||
|
|
"See also 'sleepmask'.");
|
||
|
|
#endif /* CONFIG_LOW_POWER_IDLE */
|