380 lines
8.4 KiB
C
380 lines
8.4 KiB
C
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/* Copyright 2013 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* System module for Chrome EC : MEC1322 hardware specific implementation */
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#include "clock.h"
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#include "common.h"
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#include "console.h"
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#include "cpu.h"
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#include "gpio.h"
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#include "host_command.h"
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#include "registers.h"
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#include "shared_mem.h"
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#include "system.h"
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#include "hooks.h"
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#include "task.h"
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#include "timer.h"
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#include "util.h"
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#include "spi.h"
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/* Indices for hibernate data registers (RAM backed by VBAT) */
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enum hibdata_index {
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HIBDATA_INDEX_SCRATCHPAD = 0, /* General-purpose scratchpad */
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HIBDATA_INDEX_SAVED_RESET_FLAGS, /* Saved reset flags */
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HIBDATA_INDEX_PD0, /* USB-PD0 saved port state */
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HIBDATA_INDEX_PD1, /* USB-PD1 saved port state */
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HIBDATA_INDEX_PD2, /* USB-PD2 saved port state */
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};
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static void check_reset_cause(void)
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{
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uint32_t status = MEC1322_VBAT_STS;
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uint32_t flags = 0;
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uint32_t rst_sts = MEC1322_PCR_CHIP_PWR_RST &
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(MEC1322_PWR_RST_STS_VCC1 |
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MEC1322_PWR_RST_STS_VBAT);
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/* Clear the reset causes now that we've read them */
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MEC1322_VBAT_STS |= status;
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MEC1322_PCR_CHIP_PWR_RST |= rst_sts;
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/*
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* BIT[6] determine VCC1 reset
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*/
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if (rst_sts & MEC1322_PWR_RST_STS_VCC1)
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flags |= EC_RESET_FLAG_RESET_PIN;
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flags |= MEC1322_VBAT_RAM(HIBDATA_INDEX_SAVED_RESET_FLAGS);
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MEC1322_VBAT_RAM(HIBDATA_INDEX_SAVED_RESET_FLAGS) = 0;
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if ((status & MEC1322_VBAT_STS_WDT) && !(flags & (EC_RESET_FLAG_SOFT |
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EC_RESET_FLAG_HARD |
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EC_RESET_FLAG_HIBERNATE)))
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flags |= EC_RESET_FLAG_WATCHDOG;
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system_set_reset_flags(flags);
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}
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int system_is_reboot_warm(void)
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{
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uint32_t reset_flags;
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/*
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* Check reset cause here,
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* gpio_pre_init is executed faster than system_pre_init
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*/
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check_reset_cause();
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reset_flags = system_get_reset_flags();
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if ((reset_flags & EC_RESET_FLAG_RESET_PIN) ||
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(reset_flags & EC_RESET_FLAG_POWER_ON) ||
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(reset_flags & EC_RESET_FLAG_WATCHDOG) ||
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(reset_flags & EC_RESET_FLAG_HARD) ||
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(reset_flags & EC_RESET_FLAG_SOFT) ||
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(reset_flags & EC_RESET_FLAG_HIBERNATE))
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return 0;
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else
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return 1;
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}
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void system_pre_init(void)
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{
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/* Enable direct NVIC */
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MEC1322_EC_INT_CTRL |= 1;
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/* Disable ARM TRACE debug port */
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MEC1322_EC_TRACE_EN &= ~1;
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/* Deassert nSIO_RESET */
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MEC1322_PCR_PWR_RST_CTL &= ~BIT(0);
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spi_enable(CONFIG_SPI_FLASH_PORT, 1);
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}
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void chip_save_reset_flags(uint32_t flags)
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{
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MEC1322_VBAT_RAM(HIBDATA_INDEX_SAVED_RESET_FLAGS) = flags;
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}
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uint32_t chip_read_reset_flags(void)
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{
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return MEC1322_VBAT_RAM(HIBDATA_INDEX_SAVED_RESET_FLAGS);
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}
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__attribute__((noreturn))
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void _system_reset(int flags, int wake_from_hibernate)
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{
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uint32_t save_flags = 0;
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/* Disable interrupts to avoid task swaps during reboot */
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interrupt_disable();
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/* Save current reset reasons if necessary */
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if (flags & SYSTEM_RESET_PRESERVE_FLAGS)
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save_flags = system_get_reset_flags() | EC_RESET_FLAG_PRESERVED;
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if (flags & SYSTEM_RESET_LEAVE_AP_OFF)
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save_flags |= EC_RESET_FLAG_AP_OFF;
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if (wake_from_hibernate)
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save_flags |= EC_RESET_FLAG_HIBERNATE;
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else if (flags & SYSTEM_RESET_HARD)
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save_flags |= EC_RESET_FLAG_HARD;
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else
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save_flags |= EC_RESET_FLAG_SOFT;
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chip_save_reset_flags(save_flags);
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/* Trigger watchdog in 1ms */
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MEC1322_WDG_LOAD = 1;
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MEC1322_WDG_CTL |= 1;
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/* Spin and wait for reboot; should never return */
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while (1)
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;
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}
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void system_reset(int flags)
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{
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_system_reset(flags, 0);
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}
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const char *system_get_chip_vendor(void)
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{
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return "smsc";
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}
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const char *system_get_chip_name(void)
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{
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switch (MEC1322_CHIP_DEV_ID) {
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case 0x15:
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return "mec1322";
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default:
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return "unknown";
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}
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}
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static char to_hex(int x)
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{
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if (x >= 0 && x <= 9)
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return '0' + x;
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return 'a' + x - 10;
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}
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const char *system_get_chip_revision(void)
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{
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static char buf[3];
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uint8_t rev = MEC1322_CHIP_DEV_REV;
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buf[0] = to_hex(rev / 16);
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buf[1] = to_hex(rev & 0xf);
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buf[2] = '\0';
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return buf;
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}
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static int bbram_idx_lookup(enum system_bbram_idx idx)
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{
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switch (idx) {
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case SYSTEM_BBRAM_IDX_PD0:
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return HIBDATA_INDEX_PD0;
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case SYSTEM_BBRAM_IDX_PD1:
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return HIBDATA_INDEX_PD1;
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case SYSTEM_BBRAM_IDX_PD2:
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return HIBDATA_INDEX_PD2;
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default:
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return -1;
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}
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}
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int system_get_bbram(enum system_bbram_idx idx, uint8_t *value)
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{
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int hibdata = bbram_idx_lookup(idx);
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if (hibdata < 0)
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return EC_ERROR_UNIMPLEMENTED;
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*value = MEC1322_VBAT_RAM(hibdata);
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return EC_SUCCESS;
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}
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int system_set_bbram(enum system_bbram_idx idx, uint8_t value)
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{
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int hibdata = bbram_idx_lookup(idx);
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if (hibdata < 0)
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return EC_ERROR_UNIMPLEMENTED;
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MEC1322_VBAT_RAM(hibdata) = value;
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return EC_SUCCESS;
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}
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int system_set_scratchpad(uint32_t value)
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{
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MEC1322_VBAT_RAM(HIBDATA_INDEX_SCRATCHPAD) = value;
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return EC_SUCCESS;
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}
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uint32_t system_get_scratchpad(void)
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{
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return MEC1322_VBAT_RAM(HIBDATA_INDEX_SCRATCHPAD);
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}
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void system_hibernate(uint32_t seconds, uint32_t microseconds)
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{
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int i;
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#ifdef CONFIG_HOSTCMD_PD
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/* Inform the PD MCU that we are going to hibernate. */
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host_command_pd_request_hibernate();
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/* Wait to ensure exchange with PD before hibernating. */
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msleep(100);
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#endif
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cflush();
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if (board_hibernate)
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board_hibernate();
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/* Disable interrupts */
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interrupt_disable();
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for (i = 0; i <= 92; ++i) {
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task_disable_irq(i);
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task_clear_pending_irq(i);
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}
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for (i = 8; i <= 23; ++i)
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MEC1322_INT_DISABLE(i) = 0xffffffff;
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MEC1322_INT_BLK_DIS |= 0xffff00;
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/* Power down ADC VREF */
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MEC1322_EC_ADC_VREF_PD |= 1;
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/* Assert nSIO_RESET */
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MEC1322_PCR_PWR_RST_CTL |= 1;
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/* Disable UART */
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MEC1322_UART_ACT &= ~0x1;
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MEC1322_LPC_ACT &= ~0x1;
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/* Disable JTAG */
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MEC1322_EC_JTAG_EN &= ~1;
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/* Disable 32KHz clock */
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MEC1322_VBAT_CE &= ~0x2;
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/* Stop watchdog */
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MEC1322_WDG_CTL &= ~1;
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/* Stop timers */
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MEC1322_TMR32_CTL(0) &= ~1;
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MEC1322_TMR32_CTL(1) &= ~1;
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MEC1322_TMR16_CTL(0) &= ~1;
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/* Power down ADC */
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MEC1322_ADC_CTRL &= ~1;
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/* Disable blocks */
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MEC1322_PCR_CHIP_SLP_EN |= 0x3;
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MEC1322_PCR_EC_SLP_EN |= MEC1322_PCR_EC_SLP_EN_SLEEP;
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MEC1322_PCR_HOST_SLP_EN |= MEC1322_PCR_HOST_SLP_EN_SLEEP;
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MEC1322_PCR_EC_SLP_EN2 |= MEC1322_PCR_EC_SLP_EN2_SLEEP;
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MEC1322_PCR_SLOW_CLK_CTL &= 0xfffffc00;
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/* Set sleep state */
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MEC1322_PCR_SYS_SLP_CTL = (MEC1322_PCR_SYS_SLP_CTL & ~0x7) | 0x2;
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CPU_SCB_SYSCTRL |= 0x4;
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/* Setup GPIOs for hibernate */
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if (board_hibernate_late)
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board_hibernate_late();
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#ifdef CONFIG_USB_PD_PORT_COUNT
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/*
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* Leave USB-C charging enabled in hibernate, in order to
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* allow wake-on-plug. 5V enable must be pulled low.
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*/
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#if CONFIG_USB_PD_PORT_COUNT > 0
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gpio_set_flags(GPIO_USB_C0_5V_EN, GPIO_PULL_DOWN | GPIO_INPUT);
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gpio_set_level(GPIO_USB_C0_CHARGE_EN_L, 0);
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#endif
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#if CONFIG_USB_PD_PORT_COUNT > 1
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gpio_set_flags(GPIO_USB_C1_5V_EN, GPIO_PULL_DOWN | GPIO_INPUT);
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gpio_set_level(GPIO_USB_C1_CHARGE_EN_L, 0);
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#endif
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#endif /* CONFIG_USB_PD_PORT_COUNT */
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if (hibernate_wake_pins_used > 0) {
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for (i = 0; i < hibernate_wake_pins_used; ++i) {
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const enum gpio_signal pin = hibernate_wake_pins[i];
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gpio_reset(pin);
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gpio_enable_interrupt(pin);
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}
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interrupt_enable();
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task_enable_irq(MEC1322_IRQ_GIRQ8);
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task_enable_irq(MEC1322_IRQ_GIRQ9);
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task_enable_irq(MEC1322_IRQ_GIRQ10);
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task_enable_irq(MEC1322_IRQ_GIRQ11);
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task_enable_irq(MEC1322_IRQ_GIRQ20);
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}
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if (seconds || microseconds) {
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MEC1322_INT_BLK_EN |= BIT(17);
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MEC1322_INT_ENABLE(17) |= BIT(20);
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interrupt_enable();
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task_enable_irq(MEC1322_IRQ_HTIMER);
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if (seconds > 2) {
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ASSERT(seconds <= 0xffff / 8);
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MEC1322_HTIMER_CONTROL = 1;
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MEC1322_HTIMER_PRELOAD =
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(seconds * 8 + microseconds / 125000);
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} else {
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MEC1322_HTIMER_CONTROL = 0;
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MEC1322_HTIMER_PRELOAD =
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(seconds * 1000000 + microseconds) * 2 / 71;
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}
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}
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asm("wfi");
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/* Use 48MHz clock to speed through wake-up */
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MEC1322_PCR_PROC_CLK_CTL = 1;
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/* Reboot */
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_system_reset(0, 1);
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/* We should never get here. */
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while (1)
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;
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}
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void htimer_interrupt(void)
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{
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/* Time to wake up */
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}
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DECLARE_IRQ(MEC1322_IRQ_HTIMER, htimer_interrupt, 1);
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enum system_image_copy_t system_get_shrspi_image_copy(void)
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{
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return MEC1322_VBAT_RAM(MEC1322_IMAGETYPE_IDX);
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}
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uint32_t system_get_lfw_address(void)
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{
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uint32_t * const lfw_vector =
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(uint32_t * const)CONFIG_PROGRAM_MEMORY_BASE;
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return *(lfw_vector + 1);
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}
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void system_set_image_copy(enum system_image_copy_t copy)
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{
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MEC1322_VBAT_RAM(MEC1322_IMAGETYPE_IDX) = (copy == SYSTEM_IMAGE_RW) ?
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SYSTEM_IMAGE_RW : SYSTEM_IMAGE_RO;
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}
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