360 lines
9.0 KiB
C
360 lines
9.0 KiB
C
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/* Copyright 2018 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* Clocks, PLL and power settings */
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#include "clock.h"
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#include "clock_chip.h"
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#include "common.h"
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#include "console.h"
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#include "registers.h"
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#include "task.h"
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#include "timer.h"
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#include "util.h"
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#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ## args)
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#define ULPOSC_DIV_MAX (1 << OSC_DIV_BITS)
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#define ULPOSC_CALI_MAX (1 << OSC_CALI_BITS)
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void clock_init(void)
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{
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/* Set VREQ to HW mode */
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SCP_CPU_VREQ = CPU_VREQ_HW_MODE;
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SCP_SECURE_CTRL &= ~ENABLE_SPM_MASK_VREQ;
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/* Set DDREN auto mode */
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SCP_SYS_CTRL |= AUTO_DDREN;
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/* Initialize 26MHz system clock counter reset value to 1. */
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SCP_CLK_SYS_VAL =
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(SCP_CLK_SYS_VAL & ~CLK_SYS_VAL_MASK) | CLK_SYS_VAL(1);
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/* Initialize high frequency ULPOSC counter reset value to 1. */
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SCP_CLK_HIGH_VAL =
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(SCP_CLK_HIGH_VAL & ~CLK_HIGH_VAL_MASK) | CLK_HIGH_VAL(1);
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/* Initialize sleep mode control VREQ counter. */
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SCP_CLK_SLEEP_CTRL =
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(SCP_CLK_SLEEP_CTRL & ~VREQ_COUNTER_MASK) | VREQ_COUNTER_VAL(1);
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/* Set normal wake clock */
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SCP_WAKE_CKSW &= ~WAKE_CKSW_SEL_NORMAL_MASK;
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/* Enable fast wakeup support */
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SCP_CLK_SLEEP = 0;
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SCP_CLK_ON_CTRL = (SCP_CLK_ON_CTRL & ~HIGH_FINAL_VAL_MASK) |
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HIGH_FINAL_VAL_DEFAULT;
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SCP_FAST_WAKE_CNT_END =
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(SCP_FAST_WAKE_CNT_END & ~FAST_WAKE_CNT_END_MASK) |
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FAST_WAKE_CNT_END_DEFAULT;
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/* Set slow wake clock */
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SCP_WAKE_CKSW = (SCP_WAKE_CKSW & ~WAKE_CKSW_SEL_SLOW_MASK) |
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WAKE_CKSW_SEL_SLOW_DEFAULT;
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/* Select CLK_HIGH as wakeup clock */
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SCP_CLK_SLOW_SEL = (SCP_CLK_SLOW_SEL &
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~(CKSW_SEL_SLOW_MASK | CKSW_SEL_SLOW_DIV_MASK)) |
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CKSW_SEL_SLOW_ULPOSC2_CLK;
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/*
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* Set legacy wakeup
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* - disable SPM sleep control
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* - disable SCP sleep mode
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*/
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SCP_CLK_SLEEP_CTRL &= ~(EN_SLEEP_CTRL | SPM_SLEEP_MODE);
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task_enable_irq(SCP_IRQ_CLOCK);
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task_enable_irq(SCP_IRQ_CLOCK2);
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}
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static void scp_ulposc_config(int osc, uint32_t osc_div, uint32_t osc_cali)
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{
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uint32_t val;
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/* Clear all bits */
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val = 0;
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/* Enable CP */
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val |= OSC_CP_EN;
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/* Set div */
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val |= osc_div << 17;
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/* F-band = 0, I-band = 4 */
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val |= 4 << 6;
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/* Set calibration */
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val |= osc_cali;
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/* Set control register 1 */
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AP_ULPOSC_CON02(osc) = val;
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/* Set control register 2, enable div2 */
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AP_ULPOSC_CON13(osc) |= OSC_DIV2_EN;
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}
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static inline void busy_udelay(int usec)
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{
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/*
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* Delaying by busy-looping, for place that can't use udelay because of
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* the clock not configured yet. The value 28 is chosen approximately
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* from experiment.
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*/
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volatile int i = usec * 28;
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while (i--)
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;
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}
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static unsigned int scp_measure_ulposc_freq(int osc)
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{
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unsigned int result = 0;
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int cnt;
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/* Before select meter clock input, bit[1:0] = b00 */
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AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_MODE_MASK) |
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DBG_MODE_SET_CLOCK;
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/* Select source, bit[21:16] = clk_src */
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AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_BIST_SOURCE_MASK) |
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(osc == 0 ? DBG_BIST_SOURCE_ULPOSC1 :
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DBG_BIST_SOURCE_ULPOSC2);
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/* Set meter divisor to 1, bit[31:24] = b00000000 */
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AP_CLK_MISC_CFG_0 = (AP_CLK_MISC_CFG_0 & ~MISC_METER_DIVISOR_MASK) |
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MISC_METER_DIV_1;
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/* Enable frequency meter, without start */
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AP_SCP_CFG_0 |= CFG_FREQ_METER_ENABLE;
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/* Trigger frequency meter start */
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AP_SCP_CFG_0 |= CFG_FREQ_METER_RUN;
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/*
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* Frequency meter counts cycles in 1 / (26 * 1024) second period.
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* freq_in_hz = freq_counter * 26 * 1024
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*
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* The hardware takes 38us to count cycles. Delay up to 100us,
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* as busy_udelay may not be accurate when sysclk is not 26Mhz
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* (e.g. when recalibrating/measuring after boot).
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*/
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for (cnt = 100; cnt; cnt--) {
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busy_udelay(1);
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if (!(AP_SCP_CFG_0 & CFG_FREQ_METER_RUN)) {
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result = CFG_FREQ_COUNTER(AP_SCP_CFG_1);
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break;
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}
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}
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/* Disable freq meter */
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AP_SCP_CFG_0 &= ~CFG_FREQ_METER_ENABLE;
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return result;
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}
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static inline int signum(int v)
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{
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return (v > 0) - (v < 0);
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}
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static inline int abs(int v)
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{
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return (v >= 0) ? v : -v;
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}
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static int scp_ulposc_config_measure(int osc, int div, int cali)
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{
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int freq;
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scp_ulposc_config(osc, div, cali);
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freq = scp_measure_ulposc_freq(osc);
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CPRINTF("ULPOSC%d: %d %d %d (%dkHz)\n",
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osc + 1, div, cali, freq,
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freq * 26 * 1000 / 1024);
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return freq;
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}
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/**
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* Calibrate ULPOSC to target frequency.
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*
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* @param osc 0:ULPOSC1, 1:ULPOSC2
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* @param target_mhz Target frequency to set
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* @return Frequency counter output
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*
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*/
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static int scp_calibrate_ulposc(int osc, int target_mhz)
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{
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int target_freq = DIV_ROUND_NEAREST(target_mhz * 1024, 26);
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struct ulposc {
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int div; /* frequency divisor/multiplier */
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int cali; /* variable resistor calibrator */
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int freq; /* frequency counter measure result */
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} curr, prev = {0};
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enum { STAGE_DIV, STAGE_CALI } stage = STAGE_DIV;
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int param, param_max;
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curr.div = ULPOSC_DIV_MAX / 2;
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curr.cali = ULPOSC_CALI_MAX / 2;
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param = curr.div;
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param_max = ULPOSC_DIV_MAX;
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/*
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* In the loop below, linear search closest div value to get desired
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* frequency counter value. Then adjust cali to get a better result.
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* Note that this doesn't give optimal output frequency, but it's
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* usually close enough.
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* TODO(b:120176040): See if we can efficiently calibrate the clock with
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* more precision by exploring more of the cali/div space.
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*
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* The frequency function follows. Note that f is positively correlated
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* with both div and cali:
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* f(div, cali) = k1 * (div + k2) / R(cali) * C
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* Where:
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* R(cali) = k3 / (1 + k4 * (cali - k4))
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*/
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while (1) {
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curr.freq = scp_ulposc_config_measure(osc, curr.div, curr.cali);
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if (!curr.freq)
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return 0;
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/*
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* If previous and current are on either side of the desired
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* frequency, pick the closest one.
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*/
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if (prev.freq && signum(target_freq - curr.freq) !=
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signum(target_freq - prev.freq)) {
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if (abs(target_freq - prev.freq) <
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abs(target_freq - curr.freq))
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curr = prev;
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if (stage == STAGE_CALI)
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break;
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/* Switch to optimizing cali */
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stage = STAGE_CALI;
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param = curr.cali;
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param_max = ULPOSC_CALI_MAX;
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}
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prev = curr;
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param += signum(target_freq - curr.freq);
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if (param < 0 || param >= param_max)
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return 0;
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if (stage == STAGE_DIV)
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curr.div = param;
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else
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curr.cali = param;
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}
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/*
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* It's possible we end up using prev, so reset the configuration and
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* measure again.
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*/
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return scp_ulposc_config_measure(osc, curr.div, curr.cali);
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}
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static void scp_clock_high_enable(int osc)
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{
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/* Enable high speed clock */
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SCP_CLK_EN |= EN_CLK_HIGH;
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switch (osc) {
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case 0:
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/* After 25ms, enable ULPOSC */
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busy_udelay(25 * MSEC);
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SCP_CLK_EN |= CG_CLK_HIGH;
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break;
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case 1:
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/* Turn off ULPOSC2 high-core-disable switch */
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SCP_CLK_ON_CTRL &= ~HIGH_CORE_DIS_SUB;
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/* After 25ms, turn on ULPOSC2 high core clock gate */
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busy_udelay(25 * MSEC);
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SCP_CLK_HIGH_CORE |= CLK_HIGH_CORE_CG;
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break;
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default:
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break;
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}
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}
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void scp_enable_clock(void)
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{
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/* Select default CPU clock */
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SCP_CLK_SEL = CLK_SEL_SYS_26M;
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/* VREQ */
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SCP_CPU_VREQ = 0x10001;
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SCP_SECURE_CTRL &= ~ENABLE_SPM_MASK_VREQ;
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/* DDREN auto mode */
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SCP_SYS_CTRL |= AUTO_DDREN;
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/* Set settle time */
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SCP_CLK_SYS_VAL = 1; /* System clock */
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SCP_CLK_HIGH_VAL = 1; /* ULPOSC */
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SCP_CLK_SLEEP_CTRL = (SCP_CLK_SLEEP_CTRL & ~VREQ_COUNTER_MASK) | 2;
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/* Disable slow wake */
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SCP_CLK_SLEEP = SLOW_WAKE_DISABLE;
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/* Disable SPM sleep control, disable sleep mode */
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SCP_CLK_SLEEP_CTRL &= ~(SPM_SLEEP_MODE | EN_SLEEP_CTRL);
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/* Turn off ULPOSC2 */
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SCP_CLK_ON_CTRL |= HIGH_CORE_DIS_SUB;
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scp_ulposc_config(0, 12, 32);
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scp_clock_high_enable(0); /* Turn on ULPOSC1 */
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scp_ulposc_config(1, 16, 32);
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scp_clock_high_enable(1); /* Turn on ULPOSC2 */
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/* Calibrate ULPOSC */
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scp_calibrate_ulposc(0, ULPOSC1_CLOCK_MHZ);
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scp_calibrate_ulposc(1, ULPOSC2_CLOCK_MHZ);
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/* Select ULPOSC2 high speed CPU clock */
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SCP_CLK_SEL = CLK_SEL_ULPOSC_2;
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/* Enable default clock gate */
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SCP_CLK_GATE |= CG_DMA_CH3 | CG_DMA_CH2 | CG_DMA_CH1 | CG_DMA_CH0 |
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CG_I2C_M | CG_MAD_M | CG_AP2P_M;
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/* Select pwrap_ulposc */
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AP_CLK_CFG_5 = (AP_CLK_CFG_5 & ~PWRAP_ULPOSC_MASK) | OSC_D16;
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/* Enable pwrap_ulposc clock gate */
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AP_CLK_CFG_5_CLR = PWRAP_ULPOSC_CG;
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}
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void clock_control_irq(void)
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{
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/* Read ack CLK_IRQ */
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(SCP_CLK_IRQ_ACK);
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task_clear_pending_irq(SCP_IRQ_CLOCK);
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}
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DECLARE_IRQ(SCP_IRQ_CLOCK, clock_control_irq, 3);
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void clock_fast_wakeup_irq(void)
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{
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/* Ack fast wakeup */
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SCP_SLEEP_IRQ2 = 1;
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task_clear_pending_irq(SCP_IRQ_CLOCK2);
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}
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DECLARE_IRQ(SCP_IRQ_CLOCK2, clock_fast_wakeup_irq, 3);
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/* Console command */
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int command_ulposc(int argc, char *argv[])
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{
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if (argc > 1 && !strncmp(argv[1], "cal", 3)) {
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scp_calibrate_ulposc(0, ULPOSC1_CLOCK_MHZ);
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scp_calibrate_ulposc(1, ULPOSC2_CLOCK_MHZ);
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}
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/* SCP clock meter counts every (26MHz / 1024) tick */
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ccprintf("ULPOSC1 frequency: %u kHz\n",
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scp_measure_ulposc_freq(0) * 26 * 1000 / 1024);
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ccprintf("ULPOSC2 frequency: %u kHz\n",
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scp_measure_ulposc_freq(1) * 26 * 1000 / 1024);
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return EC_SUCCESS;
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}
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DECLARE_CONSOLE_COMMAND(ulposc, command_ulposc, "[calibrate]",
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"Calibrate ULPOSC frequency");
|