309 lines
7.3 KiB
C
309 lines
7.3 KiB
C
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/* Copyright 2014 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#include "common.h"
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#include "gpio.h"
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#include "hooks.h"
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#include "registers.h"
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#include "task.h"
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#include "util.h"
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/*
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* For each interrupt (INT0-INT3, PORT), record which GPIO entry uses it.
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*/
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static const struct gpio_info *gpio_ints[NRF51_GPIOTE_IN_COUNT];
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static const struct gpio_info *gpio_int_port;
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volatile uint32_t * const nrf51_alt_funcs[] = {
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/* UART */
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&NRF51_UART_PSELRTS,
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&NRF51_UART_PSELTXD,
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&NRF51_UART_PSELCTS,
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&NRF51_UART_PSELRXD,
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/* SPI1 (SPI Master) */
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&NRF51_SPI0_PSELSCK,
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&NRF51_SPI0_PSELMOSI,
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&NRF51_SPI0_PSELMISO,
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/* TWI0 (I2C) */
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&NRF51_TWI0_PSELSCL,
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&NRF51_TWI0_PSELSDA,
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/* SPI1 (SPI Master) */
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&NRF51_SPI1_PSELSCK,
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&NRF51_SPI1_PSELMOSI,
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&NRF51_SPI1_PSELMISO,
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/* TWI1 (I2C) */
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&NRF51_TWI1_PSELSCL,
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&NRF51_TWI1_PSELSDA,
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/* SPIS1 (SPI SLAVE) */
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&NRF51_SPIS1_PSELSCK,
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&NRF51_SPIS1_PSELMISO,
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&NRF51_SPIS1_PSELMOSI,
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&NRF51_SPIS1_PSELCSN,
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/* QDEC (ROTARY DECODER) */
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&NRF51_QDEC_PSELLED,
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&NRF51_QDEC_PSELA,
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&NRF51_QDEC_PSELB,
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/* LPCOMP (Low Power Comparator) */
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&NRF51_LPCOMP_PSEL,
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};
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const unsigned int nrf51_alt_func_count = ARRAY_SIZE(nrf51_alt_funcs);
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/* Make sure the function table and defines stay in sync */
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BUILD_ASSERT(NRF51_MAX_ALT_FUNCS == ARRAY_SIZE(nrf51_alt_funcs));
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void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
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{
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uint32_t val = 0;
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uint32_t bit = GPIO_MASK_TO_NUM(mask);
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if (flags & GPIO_OUTPUT)
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val |= NRF51_PIN_CNF_DIR_OUTPUT;
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else if (flags & GPIO_INPUT)
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val |= NRF51_PIN_CNF_DIR_INPUT;
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if (flags & GPIO_PULL_DOWN)
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val |= NRF51_PIN_CNF_PULLDOWN;
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else if (flags & GPIO_PULL_UP)
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val |= NRF51_PIN_CNF_PULLUP;
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/* TODO: Drive strength? H0D1? */
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if (flags & GPIO_OPEN_DRAIN)
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val |= NRF51_PIN_CNF_DRIVE_S0D1;
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if (flags & GPIO_OUTPUT) {
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if (flags & GPIO_HIGH)
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NRF51_GPIO0_OUTSET = mask;
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else if (flags & GPIO_LOW)
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NRF51_GPIO0_OUTCLR = mask;
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}
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/* Interrupt levels */
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if (flags & GPIO_INT_SHARED) {
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/*
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* There are no shared edge-triggered interrupts;
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* they're either high or low.
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*/
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ASSERT((flags & (GPIO_INT_F_RISING | GPIO_INT_F_FALLING)) == 0);
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ASSERT((flags & GPIO_INT_LEVEL) != GPIO_INT_LEVEL);
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if (flags & GPIO_INT_F_LOW)
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val |= NRF51_PIN_CNF_SENSE_LOW;
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else if (flags & GPIO_INT_F_HIGH)
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val |= NRF51_PIN_CNF_SENSE_HIGH;
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}
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NRF51_PIN_CNF(bit) = val;
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}
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static void gpio_init(void)
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{
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task_enable_irq(NRF51_PERID_GPIOTE);
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}
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DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
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test_mockable int gpio_get_level(enum gpio_signal signal)
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{
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return !!(NRF51_GPIO0_IN & gpio_list[signal].mask);
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}
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void gpio_set_level(enum gpio_signal signal, int value)
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{
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if (value)
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NRF51_GPIO0_OUTSET = gpio_list[signal].mask;
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else
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NRF51_GPIO0_OUTCLR = gpio_list[signal].mask;
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}
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void gpio_pre_init(void)
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{
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const struct gpio_info *g = gpio_list;
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int is_warm = 0;
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int i;
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if (NRF51_POWER_RESETREAS &
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(NRF51_POWER_RESETREAS_OFF | /* GPIO Wake */
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NRF51_POWER_RESETREAS_LPCOMP)) {
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/* This is a warm reboot */
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is_warm = 1;
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}
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/* Initialize Interrupt configuration */
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for (i = 0; i < NRF51_GPIOTE_IN_COUNT; i++)
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gpio_ints[i] = NULL;
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gpio_int_port = NULL;
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/* Set all GPIOs to defaults */
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for (i = 0; i < GPIO_COUNT; i++, g++) {
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int flags = g->flags;
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if (flags & GPIO_DEFAULT)
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continue;
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/*
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* If this is a warm reboot, don't set the output levels again.
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*/
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if (is_warm)
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flags &= ~(GPIO_LOW | GPIO_HIGH);
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/* Set up GPIO based on flags */
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gpio_set_flags_by_mask(g->port, g->mask, flags);
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}
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}
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/*
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* NRF51 doesn't have an alternate function table.
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* Use the pin select registers in place of the function number.
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*/
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void gpio_set_alternate_function(uint32_t port, uint32_t mask, int func)
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{
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uint32_t bit = GPIO_MASK_TO_NUM(mask);
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ASSERT((~mask & BIT(bit)) == 0); /* Only one bit set. */
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ASSERT(port == GPIO_0);
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ASSERT((func >= 0 && func < nrf51_alt_func_count) || func == -1);
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/* Remove the previous setting(s) */
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if (func == -1) {
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int i;
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for (i = 0; i < nrf51_alt_func_count; i++) {
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if (*(nrf51_alt_funcs[i]) == bit)
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*(nrf51_alt_funcs[i]) = 0xffffffff;
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}
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} else {
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*(nrf51_alt_funcs[func]) = bit;
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}
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}
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/*
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* Enable the interrupt associated with the "signal"
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* The architecture has one general (PORT)
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* and NRF51_GPIOTE_IN_COUNT single-pin (IN0, IN1, ...) interrupts.
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*
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*/
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int gpio_enable_interrupt(enum gpio_signal signal)
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{
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int pin;
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const struct gpio_info *g = gpio_list + signal;
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/* Fail if not implemented or no interrupt handler */
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if (!g->mask || signal >= GPIO_IH_COUNT)
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return EC_ERROR_INVAL;
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/* If it's not shared, use INT0-INT3, otherwise use PORT. */
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if (!(g->flags & GPIO_INT_SHARED)) {
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int int_num, free_slot = -1;
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uint32_t event_config = 0;
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for (int_num = 0; int_num < NRF51_GPIOTE_IN_COUNT; int_num++) {
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if (gpio_ints[int_num] == g)
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return EC_SUCCESS; /* This is already set up. */
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if (gpio_ints[int_num] == NULL && free_slot == -1)
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free_slot = int_num;
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}
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ASSERT(free_slot != -1);
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gpio_ints[free_slot] = g;
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pin = GPIO_MASK_TO_NUM(g->mask);
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event_config = (pin << NRF51_GPIOTE_PSEL_POS) |
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NRF51_GPIOTE_MODE_EVENT;
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ASSERT(g->flags & (GPIO_INT_F_RISING | GPIO_INT_F_FALLING));
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/* RISING | FALLING = TOGGLE */
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if (g->flags & GPIO_INT_F_RISING)
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event_config |= NRF51_GPIOTE_POLARITY_LOTOHI;
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if (g->flags & GPIO_INT_F_FALLING)
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event_config |= NRF51_GPIOTE_POLARITY_HITOLO;
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NRF51_GPIOTE_CONFIG(free_slot) = event_config;
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/* Enable the IN[] interrupt. */
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NRF51_GPIOTE_INTENSET = 1 << free_slot;
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} else {
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/* The first handler for the shared interrupt wins. */
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if (gpio_int_port == NULL) {
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gpio_int_port = g;
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/* Enable the PORT interrupt. */
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NRF51_GPIOTE_INTENSET = 1 << NRF51_GPIOTE_PORT_BIT;
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}
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}
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return EC_SUCCESS;
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}
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/*
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* Disable the interrupt associated with the "signal"
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* The architecture has one general (PORT)
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* and NRF51_GPIOTE_IN_COUNT single-pin (IN0, IN1, ...) interrupts.
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*/
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int gpio_disable_interrupt(enum gpio_signal signal)
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{
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const struct gpio_info *g = gpio_list + signal;
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int i;
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/* Fail if not implemented or no interrupt handler */
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if (!g->mask || signal >= GPIO_IH_COUNT)
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return EC_ERROR_INVAL;
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/* If it's not shared, use INT0-INT3, otherwise use PORT. */
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if (!(g->flags & GPIO_INT_SHARED)) {
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for (i = 0; i < NRF51_GPIOTE_IN_COUNT; i++) {
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/* Remove matching handler. */
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if (gpio_ints[i] == g) {
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/* Disable the interrupt */
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NRF51_GPIOTE_INTENCLR =
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1 << NRF51_GPIOTE_IN_BIT(i);
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/* Zero the handler */
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gpio_ints[i] = NULL;
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}
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}
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} else {
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/* Disable the interrupt */
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NRF51_GPIOTE_INTENCLR = 1 << NRF51_GPIOTE_PORT_BIT;
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/* Zero the shared handler */
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gpio_int_port = NULL;
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}
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return EC_SUCCESS;
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}
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/*
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* Clear interrupt and run handler.
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*/
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void gpio_interrupt(void)
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{
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const struct gpio_info *g;
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int i;
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int signal;
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for (i = 0; i < NRF51_GPIOTE_IN_COUNT; i++) {
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if (NRF51_GPIOTE_IN(i)) {
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NRF51_GPIOTE_IN(i) = 0;
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g = gpio_ints[i];
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signal = g - gpio_list;
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if (g && signal < GPIO_IH_COUNT)
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gpio_irq_handlers[signal](signal);
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}
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}
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if (NRF51_GPIOTE_PORT) {
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NRF51_GPIOTE_PORT = 0;
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g = gpio_int_port;
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signal = g - gpio_list;
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if (g && signal < GPIO_IH_COUNT)
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gpio_irq_handlers[signal](signal);
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}
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}
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DECLARE_IRQ(NRF51_PERID_GPIOTE, gpio_interrupt, 1);
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