120 lines
3.0 KiB
ArmAsm
120 lines
3.0 KiB
ArmAsm
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/* Copyright 2016 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*
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* x86 task swtching and interrupt handling
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*/
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#include "config.h"
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#include "registers.h"
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#include "task_defs.h"
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#include "irq_handler_common.S"
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.text
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.extern current_task
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.extern next_task
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.global __task_start
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.global __switchto
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.global default_int_handler
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.global sw_irq_handler
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# Start the task scheduling. Start current_task (hook_task)
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# This function is not an ISR but imitates the sequence.
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.align 4
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.func __task_start
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__task_start:
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movl 0x4(%esp), %ecx
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movl current_task, %eax
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movl (%eax), %esp
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#ifdef CONFIG_FPU
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movl USE_FPU_OFFSET(%eax), %ebx
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test %ebx, %ebx
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jz 1f
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frstor FPU_CTX_OFFSET(%eax)
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1:
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#endif
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movl $0x1, (%ecx) # first task is ready. set start_called = 1
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popa
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iret
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.endfunc
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# Default interrupt handler - to handle exceptions
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# and prints error
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.align 4
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.func default_int_handler
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default_int_handler:
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pusha
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ASM_LOCK_PREFIX addl $1, __in_isr
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movl %esp, %eax
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movl $stack_end, %esp # use system stack
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push %eax # push sp of preempted context
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call unhandled_vector # Handle system interrupts and
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# unregistered user interrupts
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pop %esp # restore sp of preempted context
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# unhandled_vector call loads eax with vector for comparison
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cmpl $LAPIC_SPURIOUS_INT_VECTOR, %eax
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je 1f # No EOI for LAPIC_SPURIOUS_INT_VECTOR
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movl %eax, IOAPIC_EOI_REG_ADDR # Indicate completion of servicing the
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# interrupt to IOAPIC first
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movl $0x00, LAPIC_EOI_REG_ADDR # Indicate completion of servicing the
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# interrupt to LAPIC next
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1:
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# Ensure we balance the __in_isr counter
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ASM_LOCK_PREFIX subl $1, __in_isr
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popa
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iret
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.endfunc
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.align 4
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.func sw_irq_handler
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sw_irq_handler:
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pusha
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ASM_LOCK_PREFIX addl $1, __in_isr
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# Call sw irq handler with irq number(%ecx) from task_trigger_irq.
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# Pass 0 for both desched and resched since we don't need to deschedule
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# our current task (and idle task can always be rescheduled)
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irq_handler_common $0 $0 %ecx
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# Indicate completion of servicing the interrupt to LAPIC.
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# No IOAPIC EOI needed as this is SW triggered.
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movl $0x00, LAPIC_EOI_REG_ADDR
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# Decrement ISR counter and restore general purpose registers.
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ASM_LOCK_PREFIX subl $1, __in_isr
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popa
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iret
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.endfunc
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# Switches from one task to another if ready.
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# __schedule triggers software interrupt ISH_TS_VECTOR, which is handled by
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# __switchto
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.align 4
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.func __switchto
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__switchto:
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pusha
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ASM_LOCK_PREFIX addl $1, __in_isr
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# __schedule() copies 'resched' to %ecx and 'desched' to %edx before
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# triggering ISH_TS_VECTOR.
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# Call sw_irq with an invalid IRQ so it will skip calling a routine
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irq_handler_common %edx %ecx $CONFIG_IRQ_COUNT
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# Indicate completion of servicing the interrupt to LAPIC.
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# No IOAPIC EOI needed as this is SW triggered.
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movl $0x00, LAPIC_EOI_REG_ADDR
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# Decrement ISR counter and restore general purpose registers.
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ASM_LOCK_PREFIX subl $1, __in_isr
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popa
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iret
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.endfunc
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