90 lines
3.0 KiB
C
90 lines
3.0 KiB
C
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/* Copyright 2012 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*
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* i8042 keyboard protocol constants
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*/
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#ifndef __CROS_EC_I8042_PROTOCOL_H
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#define __CROS_EC_I8042_PROTOCOL_H
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/* Some commands appear more than once. Why? */
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/* port 0x60 */
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#define I8042_CMD_MOUSE_1_1 0xe6
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#define I8042_CMD_MOUSE_2_1 0xe7
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#define I8042_CMD_MOUSE_RES 0xe8
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#define I8042_CMD_OK_GETID 0xe8
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#define I8042_CMD_GET_MOUSE 0xe9
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#define I8042_CMD_EX_ENABLE 0xea
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#define I8042_CMD_EX_SETLEDS 0xeb
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#define I8042_CMD_SETLEDS 0xed
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#define I8042_CMD_DIAG_ECHO 0xee
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#define I8042_CMD_GSCANSET 0xf0
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#define I8042_CMD_SSCANSET 0xf0
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#define I8042_CMD_GETID 0xf2
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#define I8042_CMD_SETREP 0xf3
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#define I8042_CMD_ENABLE 0xf4
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#define I8042_CMD_RESET_DIS 0xf5
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#define I8042_CMD_RESET_DEF 0xf6
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#define I8042_CMD_ALL_TYPEM 0xf7
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#define I8042_CMD_SETALL_MB 0xf8
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#define I8042_CMD_SETALL_MBR 0xfa
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#define I8042_CMD_SET_A_KEY_T 0xfb
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#define I8042_CMD_SET_A_KEY_MR 0xfc
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#define I8042_CMD_SET_A_KEY_M 0xfd
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#define I8042_CMD_RESET 0xff
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#define I8042_CMD_RESEND 0xfe
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/* port 0x64 */
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#define I8042_READ_CMD_BYTE 0x20
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#define I8042_READ_CTL_RAM 0x21
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#define I8042_READ_CTL_RAM_END 0x3f
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#define I8042_WRITE_CMD_BYTE 0x60 /* expect a byte on port 0x60 */
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#define I8042_WRITE_CTL_RAM 0x61
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#define I8042_WRITE_CTL_RAM_END 0x7f
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#define I8042_ROUTE_AUX0 0x90
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#define I8042_ROUTE_AUX1 0x91
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#define I8042_ROUTE_AUX2 0x92
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#define I8042_ROUTE_AUX3 0x93
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#define I8042_ENA_PASSWORD 0xa6
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#define I8042_DIS_MOUSE 0xa7
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#define I8042_ENA_MOUSE 0xa8
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#define I8042_TEST_MOUSE 0xa9
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#define I8042_RESET_SELF_TEST 0xaa
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#define I8042_TEST_KB_PORT 0xab
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#define I8042_DIS_KB 0xad
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#define I8042_ENA_KB 0xae
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#define I8042_READ_OUTPUT_PORT 0xd0
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#define I8042_WRITE_OUTPUT_PORT 0xd1
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#define I8042_ECHO_MOUSE 0xd3 /* expect a byte on port 0x60 */
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#define I8042_SEND_TO_MOUSE 0xd4 /* expect a byte on port 0x60 */
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#define I8042_DISABLE_A20 0xdd
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#define I8042_ENABLE_A20 0xdf
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#define I8042_PULSE_START 0xf0
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#define I8042_SYSTEM_RESET 0xfe
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#define I8042_PULSE_END 0xff
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/* port 0x60 return value */
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#define I8042_RET_EMUL0 0xe0
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#define I8042_RET_EMUL1 0xe1
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#define I8042_RET_ECHO 0xee
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#define I8042_RET_RELEASE 0xf0
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#define I8042_RET_HANJA 0xf1
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#define I8042_RET_HANGEUL 0xf2
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#define I8042_RET_ACK 0xfa
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#define I8042_RET_TEST_FAIL 0xfc
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#define I8042_RET_INTERNAL_FAIL 0xfd
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#define I8042_RET_NAK 0xfe
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#define I8042_RET_ERR 0xff
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/* port 64 - command byte bits */
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#define I8042_XLATE BIT(6)
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#define I8042_AUX_DIS BIT(5)
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#define I8042_KBD_DIS BIT(4)
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#define I8042_SYS_FLAG BIT(2)
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#define I8042_ENIRQ12 BIT(1)
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#define I8042_ENIRQ1 BIT(0)
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#endif /* __CROS_EC_I8042_PROTOCOL_H */
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