61 lines
1.4 KiB
C
61 lines
1.4 KiB
C
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/* Copyright 2016 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* Intel X86 chipset power control module for Chrome EC */
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#ifndef __CROS_EC_INTEL_X86_H
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#define __CROS_EC_INTEL_X86_H
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#include "espi.h"
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#include "power.h"
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/* Chipset specific header files */
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/* Geminilake and apollolake use same power sequencing. */
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#ifdef CONFIG_CHIPSET_APL_GLK
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#include "apollolake.h"
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#elif defined(CONFIG_CHIPSET_CANNONLAKE)
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#include "cannonlake.h"
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#elif defined(CONFIG_CHIPSET_COMETLAKE)
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#include "cometlake.h"
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#elif defined(CONFIG_CHIPSET_ICL_TGL)
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#include "icelake.h"
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#elif defined(CONFIG_CHIPSET_SKYLAKE)
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#include "skylake.h"
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#endif
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/* GPIO for power signal */
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#ifdef CONFIG_HOSTCMD_ESPI_VW_SLP_SIGNALS
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#define SLP_S3_SIGNAL_L VW_SLP_S3_L
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#define SLP_S4_SIGNAL_L VW_SLP_S4_L
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#else
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#define SLP_S3_SIGNAL_L GPIO_PCH_SLP_S3_L
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#define SLP_S4_SIGNAL_L GPIO_PCH_SLP_S4_L
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#endif
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/**
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* Handle RSMRST signal.
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*
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* @param state Current chipset state.
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*/
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void common_intel_x86_handle_rsmrst(enum power_state state);
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/**
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* Force chipset to G3 state.
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*
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* @return power_state New chipset state.
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*/
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enum power_state chipset_force_g3(void);
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/**
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* Handle power states.
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*
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* @param state Current chipset state.
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* @return power_state New chipset state.
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*/
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enum power_state common_intel_x86_power_handle_state(enum power_state state);
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#endif /* __CROS_EC_INTEL_X86_H */
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