58 lines
1.5 KiB
C
58 lines
1.5 KiB
C
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/* Copyright 2016 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* Skylake IMVP8 / ROP PMIC chipset power control module for Chrome EC */
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#ifndef __CROS_EC_SKYLAKE_H
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#define __CROS_EC_SKYLAKE_H
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/*
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* Input state flags.
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* TODO: Normalize the power signal masks from board defines to SoC headers.
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*/
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#define IN_PCH_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED)
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#define IN_PCH_SLP_S4_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED)
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#define IN_PCH_SLP_SUS_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_SUS_DEASSERTED)
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#define IN_ALL_PM_SLP_DEASSERTED (IN_PCH_SLP_S3_DEASSERTED | \
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IN_PCH_SLP_S4_DEASSERTED | \
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IN_PCH_SLP_SUS_DEASSERTED)
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/*
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* DPWROK is NC / stuffing option on initial boards.
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* TODO(shawnn): Figure out proper control signals.
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*/
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#define IN_PGOOD_ALL_CORE 0
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#define IN_ALL_S0 (IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED)
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#define CHIPSET_G3S5_POWERUP_SIGNAL IN_PCH_SLP_SUS_DEASSERTED
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#define CHARGER_INITIALIZED_DELAY_MS 100
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#define CHARGER_INITIALIZED_TRIES 40
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/* Power signals list */
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enum power_signal {
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#ifdef CONFIG_POWER_S0IX
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X86_SLP_S0_DEASSERTED,
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#endif
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X86_SLP_S3_DEASSERTED,
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X86_SLP_S4_DEASSERTED,
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X86_SLP_SUS_DEASSERTED,
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X86_RSMRST_L_PWRGD,
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X86_PMIC_DPWROK,
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/* Number of X86 signals */
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POWER_SIGNAL_COUNT
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};
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/*
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* Board can define this function to indicate to the skylake
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* power code that it does not have working reset flags.
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*/
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int board_has_working_reset_flags(void);
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#endif /* __CROS_EC_SKYLAKE_H */
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