487 lines
18 KiB
Ada
487 lines
18 KiB
Ada
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--
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-- Copyright (C) 2017 secunet Security Networks AG
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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with HW.Debug;
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with GNAT.Source_Info;
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with HW.GFX.GMA.Config;
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with HW.GFX.GMA.Registers;
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with HW.GFX.GMA.DDI_Phy;
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use HW.GFX.GMA.Registers;
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package body HW.GFX.GMA.PLLs
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with
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Refined_State => (State => null)
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is
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-- DPLL clock equation:
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-- 5 * Target_Dotclock = Ref_Clk * M1 * (M2 / 2^22) / N / (P1 * P2)
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--
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-- Where
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-- M1 = 2,
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-- Ref_Clk = 100MHz,
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-- VCO = Ref_Clk * 2 * (M2 / 2^22),
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-- N = 1 and
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-- P = P1 * P2.
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Ref_Clk : constant := 100_000_000;
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M1 : constant := 2;
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N : constant := 1;
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-- i915 has a fixme for the M2 range. But the VCO range is very
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-- limited, giving us a narrow range for M2: 24 .. 33.5
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subtype VCO_Range is Pos64 range 4_800_000_000 .. 6_700_000_000;
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subtype M2_Range is Pos64 range
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N * VCO_Range'First * 2 ** 22 / Ref_Clk / M1 ..
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N * VCO_Range'Last * 2 ** 22 / Ref_Clk / M1;
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subtype N_Range is Pos64 range 1 .. 1;
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subtype P1_Range is Pos64 range 2 .. 4;
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subtype P2_Range is Pos64 range 1 .. 20;
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subtype Clock_Range is Frequency_Type range
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Frequency_Type'First .. 540_000_000;
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subtype HDMI_Clock_Range is Clock_Range range
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25_000_000 .. Config.HDMI_Max_Clock_24bpp;
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subtype Clock_Gap is Clock_Range range 223_333_333 + 1 .. 240_000_000 - 1;
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type Clock_Type is record
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M2 : M2_Range;
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P1 : P1_Range;
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P2 : P2_Range;
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VCO : VCO_Range;
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Dotclock : Clock_Range;
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end record;
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Invalid_Clock : constant Clock_Type :=
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(M2 => M2_Range'Last,
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P1 => P1_Range'Last,
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P2 => P2_Range'Last,
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VCO => VCO_Range'Last,
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Dotclock => Clock_Range'Last);
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procedure Calculate_Clock_Parameters
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(Target_Dotclock : in HDMI_Clock_Range;
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Best_Clock : out Clock_Type;
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Valid : out Boolean)
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with
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Pre => True
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is
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Target_Clock : constant Pos64 := 5 * Target_Dotclock;
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M2, VCO, Current_Clock : Pos64;
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P2 : P2_Range;
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Valid_Clk : Boolean;
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begin
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pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
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Valid := False;
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Best_Clock := Invalid_Clock;
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-- reverse loops as hardware prefers higher values
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for P1 in reverse P1_Range loop
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-- find the highest P2 that results in valid clock
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P2 := P2_Range'Last;
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loop
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M2 := Div_Round_Closest
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(Target_Clock * P2 * P1 * N * 2 ** 22, Ref_Clk * M1);
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VCO := Div_Round_Closest (Ref_Clk * M1 * M2, 2 ** 22 * N);
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Current_Clock := Div_Round_Closest (VCO, P1 * P2);
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Valid_Clk := M2 in M2_Range and then
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Div_Round_Closest (Current_Clock, 5) in Clock_Range;
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if Valid_Clk then
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-- the error is always below 2^-22, higher P takes precedence
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if not Valid or P1 * P2 > Best_Clock.P1 * Best_Clock.P2 then
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Best_Clock := Clock_Type'
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(M2 => M2,
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P1 => P1,
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P2 => P2,
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VCO => VCO,
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Dotclock => Div_Round_Closest (Current_Clock, 5));
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Valid := True;
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end if;
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end if;
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-- Prefer higher P2 over marginal lower error. This is
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-- just an optimization, since lower P2 values would get
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-- filtered above anyway.
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exit when Valid_Clk;
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-- If M2 got too low, it won't get any better. Another
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-- optimization.
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exit when M2 < M2_Range'First;
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exit when P2 = P2_Range'First;
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if P2 > 10 then
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P2 := P2 - 2;
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else
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P2 := P2 - 1;
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end if;
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end loop;
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end loop;
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pragma Debug (Valid, Debug.Put_Line ("Valid clock found."));
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pragma Debug (Valid, Debug.Put ("M2 / P1 / P2: "));
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pragma Debug (Valid, Debug.Put_Word32 (Word32 (Best_Clock.M2)));
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pragma Debug (Valid, Debug.Put (" / "));
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pragma Debug (Valid, Debug.Put_Int8 (Pos8 (Best_Clock.P1)));
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pragma Debug (Valid, Debug.Put (" / "));
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pragma Debug (Valid, Debug.Put_Int8 (Pos8 (Best_Clock.P2)));
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pragma Debug (Valid, Debug.New_Line);
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pragma Debug (Valid, Debug.Put ("Best / Target: "));
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pragma Debug (Valid, Debug.Put_Int64 (Best_Clock.Dotclock));
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pragma Debug (Valid, Debug.Put (" / "));
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pragma Debug (Valid, Debug.Put_Int64 (Target_Dotclock));
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pragma Debug (Valid, Debug.New_Line);
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pragma Debug (not Valid, Debug.Put_Line ("No valid clock found."));
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end Calculate_Clock_Parameters;
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----------------------------------------------------------------------------
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subtype Valid_PLLs is T range DPLL_A .. DPLL_C;
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type Port_PLL_Regs is record
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PLL_ENABLE : Registers_Index;
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PLL_EBB_0 : Registers_Index;
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PLL_EBB_4 : Registers_Index;
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PLL_0 : Registers_Index;
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PLL_1 : Registers_Index;
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PLL_2 : Registers_Index;
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PLL_3 : Registers_Index;
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PLL_6 : Registers_Index;
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PLL_8 : Registers_Index;
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PLL_9 : Registers_Index;
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PLL_10 : Registers_Index;
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PCS_DW12_LN01 : Registers_Index;
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PCS_DW12_GRP : Registers_Index;
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end record;
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type Port_PLL_Array is array (Valid_PLLs) of Port_PLL_Regs;
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PORT : constant Port_PLL_Array :=
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(DPLL_A =>
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(PLL_ENABLE => BXT_PORT_PLL_ENABLE_A,
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PLL_EBB_0 => BXT_PORT_PLL_EBB_0_A,
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PLL_EBB_4 => BXT_PORT_PLL_EBB_4_A,
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PLL_0 => BXT_PORT_PLL_0_A,
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PLL_1 => BXT_PORT_PLL_1_A,
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PLL_2 => BXT_PORT_PLL_2_A,
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PLL_3 => BXT_PORT_PLL_3_A,
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PLL_6 => BXT_PORT_PLL_6_A,
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PLL_8 => BXT_PORT_PLL_8_A,
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PLL_9 => BXT_PORT_PLL_9_A,
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PLL_10 => BXT_PORT_PLL_10_A,
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PCS_DW12_LN01 => BXT_PORT_PCS_DW12_01_A,
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PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_A),
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DPLL_B =>
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(PLL_ENABLE => BXT_PORT_PLL_ENABLE_B,
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PLL_EBB_0 => BXT_PORT_PLL_EBB_0_B,
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PLL_EBB_4 => BXT_PORT_PLL_EBB_4_B,
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PLL_0 => BXT_PORT_PLL_0_B,
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PLL_1 => BXT_PORT_PLL_1_B,
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PLL_2 => BXT_PORT_PLL_2_B,
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PLL_3 => BXT_PORT_PLL_3_B,
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PLL_6 => BXT_PORT_PLL_6_B,
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PLL_8 => BXT_PORT_PLL_8_B,
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PLL_9 => BXT_PORT_PLL_9_B,
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PLL_10 => BXT_PORT_PLL_10_B,
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PCS_DW12_LN01 => BXT_PORT_PCS_DW12_01_B,
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PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_B),
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DPLL_C =>
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(PLL_ENABLE => BXT_PORT_PLL_ENABLE_C,
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PLL_EBB_0 => BXT_PORT_PLL_EBB_0_C,
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PLL_EBB_4 => BXT_PORT_PLL_EBB_4_C,
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PLL_0 => BXT_PORT_PLL_0_C,
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PLL_1 => BXT_PORT_PLL_1_C,
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PLL_2 => BXT_PORT_PLL_2_C,
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PLL_3 => BXT_PORT_PLL_3_C,
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PLL_6 => BXT_PORT_PLL_6_C,
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PLL_8 => BXT_PORT_PLL_8_C,
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PLL_9 => BXT_PORT_PLL_9_C,
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PLL_10 => BXT_PORT_PLL_10_C,
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PCS_DW12_LN01 => BXT_PORT_PCS_DW12_01_C,
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PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_C));
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PORT_PLL_ENABLE : constant := 1 * 2 ** 31;
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PORT_PLL_ENABLE_LOCK : constant := 1 * 2 ** 30;
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PORT_PLL_ENABLE_REF_SEL : constant := 1 * 2 ** 27;
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PORT_PLL_EBB0_P1_SHIFT : constant := 13;
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PORT_PLL_EBB0_P1_MASK : constant := 16#07# * 2 ** 13;
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PORT_PLL_EBB0_P2_SHIFT : constant := 8;
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PORT_PLL_EBB0_P2_MASK : constant := 16#1f# * 2 ** 8;
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function PORT_PLL_EBB0_P1 (P1 : P1_Range) return Word32 is
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begin
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return Shift_Left (Word32 (P1), PORT_PLL_EBB0_P1_SHIFT);
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end PORT_PLL_EBB0_P1;
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function PORT_PLL_EBB0_P2 (P2 : P2_Range) return Word32 is
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begin
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return Shift_Left (Word32 (P2), PORT_PLL_EBB0_P2_SHIFT);
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end PORT_PLL_EBB0_P2;
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PORT_PLL_EBB4_RECALIBRATE : constant := 1 * 2 ** 14;
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PORT_PLL_EBB4_10BIT_CLK_ENABLE : constant := 1 * 2 ** 13;
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PORT_PLL_0_M2_INT_MASK : constant := 16#ff# * 2 ** 0;
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function PORT_PLL_0_M2_INT (M2 : M2_Range) return Word32 is
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begin
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return Shift_Right (Word32 (M2), 22);
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end PORT_PLL_0_M2_INT;
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PORT_PLL_1_N_SHIFT : constant := 8;
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PORT_PLL_1_N_MASK : constant := 16#0f# * 2 ** 8;
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function PORT_PLL_1_N (N : N_Range) return Word32 is
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begin
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return Shift_Left (Word32 (N), PORT_PLL_1_N_SHIFT);
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end PORT_PLL_1_N;
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PORT_PLL_2_M2_FRAC_MASK : constant := 16#3f_ffff#;
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function PORT_PLL_2_M2_FRAC (M2 : M2_Range) return Word32 is
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begin
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return Word32 (M2) and PORT_PLL_2_M2_FRAC_MASK;
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end PORT_PLL_2_M2_FRAC;
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PORT_PLL_3_M2_FRAC_EN_MASK : constant := 1 * 2 ** 16;
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function PORT_PLL_3_M2_FRAC_EN (M2 : M2_Range) return Word32 is
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begin
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return
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(if (Word32 (M2) and PORT_PLL_2_M2_FRAC_MASK) /= 0 then
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PORT_PLL_3_M2_FRAC_EN_MASK else 0);
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end PORT_PLL_3_M2_FRAC_EN;
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PORT_PLL_6_GAIN_CTL_SHIFT : constant := 16;
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PORT_PLL_6_GAIN_CTL_MASK : constant := 16#07# * 2 ** 16;
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PORT_PLL_6_INT_COEFF_SHIFT : constant := 8;
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PORT_PLL_6_INT_COEFF_MASK : constant := 16#1f# * 2 ** 8;
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PORT_PLL_6_PROP_COEFF_MASK : constant := 16#0f# * 2 ** 0;
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function PORT_PLL_6_GAIN_COEFF (VCO : VCO_Range) return Word32 is
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begin
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return
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(if VCO >= 6_200_000_000 then
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Shift_Left (Word32'(3), PORT_PLL_6_GAIN_CTL_SHIFT) or
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Shift_Left (Word32'(9), PORT_PLL_6_INT_COEFF_SHIFT) or
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Word32'(4)
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elsif VCO /= 5_400_000_000 then
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Shift_Left (Word32'(3), PORT_PLL_6_GAIN_CTL_SHIFT) or
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Shift_Left (Word32'(11), PORT_PLL_6_INT_COEFF_SHIFT) or
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Word32'(5)
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else
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Shift_Left (Word32'(1), PORT_PLL_6_GAIN_CTL_SHIFT) or
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Shift_Left (Word32'(8), PORT_PLL_6_INT_COEFF_SHIFT) or
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Word32'(3));
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end PORT_PLL_6_GAIN_COEFF;
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PORT_PLL_8_TARGET_CNT_MASK : constant := 16#3ff#;
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function PORT_PLL_8_TARGET_CNT (VCO : VCO_Range) return Word32 is
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begin
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return (if VCO >= 6_200_000_000 then 8 else 9);
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end PORT_PLL_8_TARGET_CNT;
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PORT_PLL_9_LOCK_THRESHOLD_SHIFT : constant := 1;
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PORT_PLL_9_LOCK_THRESHOLD_MASK : constant := 16#07# * 2 ** 1;
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function PORT_PLL_9_LOCK_THRESHOLD (Threshold : Natural) return Word32 is
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begin
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return
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Shift_Left (Word32 (Threshold), PORT_PLL_9_LOCK_THRESHOLD_SHIFT) and
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PORT_PLL_9_LOCK_THRESHOLD_MASK;
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end PORT_PLL_9_LOCK_THRESHOLD;
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PORT_PLL_10_DCO_AMP_OVR_EN_H : constant := 2 ** 27;
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PORT_PLL_10_DCO_AMP_SHIFT : constant := 10;
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PORT_PLL_10_DCO_AMP_MASK : constant := 16#0f# * 2 ** 10;
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function PORT_PLL_10_DCO_AMP (Amp : Natural) return Word32 is
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begin
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return
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Shift_Left (Word32 (Amp), PORT_PLL_10_DCO_AMP_SHIFT) and
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PORT_PLL_10_DCO_AMP_MASK;
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end PORT_PLL_10_DCO_AMP;
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PORT_PCS_LANE_STAGGER_STRAP_OVRD : constant := 2 ** 6;
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PORT_PCS_LANE_STAGGER_MASK : constant := 16#1f# * 2 ** 0;
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function PORT_PCS_LANE_STAGGER (Dotclock : Clock_Range) return Word32 is
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begin
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return Word32'(PORT_PCS_LANE_STAGGER_STRAP_OVRD) or
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(if Dotclock > 270_000_000 then
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16#18#
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elsif Dotclock > 135_000_000 then
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16#0d#
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elsif Dotclock > 67_000_000 then
|
||
|
|
16#07#
|
||
|
|
elsif Dotclock > 33_000_000 then
|
||
|
|
16#04#
|
||
|
|
else
|
||
|
|
16#02#);
|
||
|
|
end PORT_PCS_LANE_STAGGER;
|
||
|
|
|
||
|
|
----------------------------------------------------------------------------
|
||
|
|
|
||
|
|
procedure Program_DPLL (P : Valid_PLLs; Clock : Clock_Type)
|
||
|
|
is
|
||
|
|
PCS : Word32;
|
||
|
|
begin
|
||
|
|
pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
|
||
|
|
|
||
|
|
Set_Mask (PORT (P).PLL_ENABLE, PORT_PLL_ENABLE_REF_SEL); -- non-SSC ref
|
||
|
|
Unset_Mask (PORT (P).PLL_EBB_4, PORT_PLL_EBB4_10BIT_CLK_ENABLE);
|
||
|
|
|
||
|
|
Unset_And_Set_Mask
|
||
|
|
(Register => PORT (P).PLL_EBB_0,
|
||
|
|
Mask_Unset => PORT_PLL_EBB0_P1_MASK or
|
||
|
|
PORT_PLL_EBB0_P2_MASK,
|
||
|
|
Mask_Set => PORT_PLL_EBB0_P1 (Clock.P1) or
|
||
|
|
PORT_PLL_EBB0_P2 (Clock.P2));
|
||
|
|
Unset_And_Set_Mask
|
||
|
|
(Register => PORT (P).PLL_0,
|
||
|
|
Mask_Unset => PORT_PLL_0_M2_INT_MASK,
|
||
|
|
Mask_Set => PORT_PLL_0_M2_INT (Clock.M2));
|
||
|
|
Unset_And_Set_Mask
|
||
|
|
(Register => PORT (P).PLL_1,
|
||
|
|
Mask_Unset => PORT_PLL_1_N_MASK,
|
||
|
|
Mask_Set => PORT_PLL_1_N (N));
|
||
|
|
Unset_And_Set_Mask
|
||
|
|
(Register => PORT (P).PLL_2,
|
||
|
|
Mask_Unset => PORT_PLL_2_M2_FRAC_MASK,
|
||
|
|
Mask_Set => PORT_PLL_2_M2_FRAC (Clock.M2));
|
||
|
|
Unset_And_Set_Mask
|
||
|
|
(Register => PORT (P).PLL_3,
|
||
|
|
Mask_Unset => PORT_PLL_3_M2_FRAC_EN_MASK,
|
||
|
|
Mask_Set => PORT_PLL_3_M2_FRAC_EN (Clock.M2));
|
||
|
|
Unset_And_Set_Mask
|
||
|
|
(Register => PORT (P).PLL_6,
|
||
|
|
Mask_Unset => PORT_PLL_6_GAIN_CTL_MASK or
|
||
|
|
PORT_PLL_6_INT_COEFF_MASK or
|
||
|
|
PORT_PLL_6_PROP_COEFF_MASK,
|
||
|
|
Mask_Set => PORT_PLL_6_GAIN_COEFF (Clock.VCO));
|
||
|
|
Unset_And_Set_Mask
|
||
|
|
(Register => PORT (P).PLL_8,
|
||
|
|
Mask_Unset => PORT_PLL_8_TARGET_CNT_MASK,
|
||
|
|
Mask_Set => PORT_PLL_8_TARGET_CNT (Clock.VCO));
|
||
|
|
Unset_And_Set_Mask
|
||
|
|
(Register => PORT (P).PLL_9,
|
||
|
|
Mask_Unset => PORT_PLL_9_LOCK_THRESHOLD_MASK,
|
||
|
|
Mask_Set => PORT_PLL_9_LOCK_THRESHOLD (5));
|
||
|
|
Unset_And_Set_Mask
|
||
|
|
(Register => PORT (P).PLL_10,
|
||
|
|
Mask_Unset => PORT_PLL_10_DCO_AMP_MASK,
|
||
|
|
Mask_Set => PORT_PLL_10_DCO_AMP_OVR_EN_H or
|
||
|
|
PORT_PLL_10_DCO_AMP (15));
|
||
|
|
|
||
|
|
Set_Mask (PORT (P).PLL_EBB_4, PORT_PLL_EBB4_RECALIBRATE);
|
||
|
|
Set_Mask (PORT (P).PLL_EBB_4, PORT_PLL_EBB4_10BIT_CLK_ENABLE);
|
||
|
|
|
||
|
|
Set_Mask (PORT (P).PLL_ENABLE, PORT_PLL_ENABLE);
|
||
|
|
Wait_Set_Mask
|
||
|
|
(Register => PORT (P).PLL_ENABLE,
|
||
|
|
Mask => PORT_PLL_ENABLE_LOCK,
|
||
|
|
TOut_MS => 1); -- 100us
|
||
|
|
|
||
|
|
Read (PORT (P).PCS_DW12_LN01, PCS);
|
||
|
|
PCS := PCS and not PORT_PCS_LANE_STAGGER_MASK;
|
||
|
|
PCS := PCS or PORT_PCS_LANE_STAGGER (Clock.Dotclock);
|
||
|
|
Write (PORT (P).PCS_DW12_GRP, PCS);
|
||
|
|
end Program_DPLL;
|
||
|
|
|
||
|
|
----------------------------------------------------------------------------
|
||
|
|
|
||
|
|
procedure Alloc
|
||
|
|
(Port_Cfg : in Port_Config;
|
||
|
|
PLL : out T;
|
||
|
|
Success : out Boolean)
|
||
|
|
is
|
||
|
|
Clock : Clock_Type := Invalid_Clock;
|
||
|
|
begin
|
||
|
|
pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
|
||
|
|
|
||
|
|
case Port_Cfg.Port is
|
||
|
|
when DIGI_A => PLL := DPLL_A;
|
||
|
|
when DIGI_B => PLL := DPLL_B;
|
||
|
|
when DIGI_C => PLL := DPLL_C;
|
||
|
|
when others => PLL := Invalid_PLL;
|
||
|
|
end case;
|
||
|
|
|
||
|
|
Success := PLL /= Invalid_PLL;
|
||
|
|
|
||
|
|
if Success then
|
||
|
|
case Port_Cfg.Display is
|
||
|
|
when DP =>
|
||
|
|
Success := True;
|
||
|
|
-- we use static values for DP
|
||
|
|
case Port_Cfg.DP.Bandwidth is
|
||
|
|
when DP_Bandwidth_1_62 =>
|
||
|
|
Clock.M2 := 32 * 2 ** 22 + 1677722;
|
||
|
|
Clock.P1 := 4;
|
||
|
|
Clock.P2 := 2;
|
||
|
|
Clock.VCO := 6_480_000_019;
|
||
|
|
Clock.Dotclock := 162_000_000;
|
||
|
|
when DP_Bandwidth_2_7 =>
|
||
|
|
Clock.M2 := 27 * 2 ** 22;
|
||
|
|
Clock.P1 := 4;
|
||
|
|
Clock.P2 := 1;
|
||
|
|
Clock.VCO := 5_400_000_000;
|
||
|
|
Clock.Dotclock := 270_000_000;
|
||
|
|
when DP_Bandwidth_5_4 =>
|
||
|
|
Clock.M2 := 27 * 2 ** 22;
|
||
|
|
Clock.P1 := 2;
|
||
|
|
Clock.P2 := 1;
|
||
|
|
Clock.VCO := 5_400_000_000;
|
||
|
|
Clock.Dotclock := 540_000_000;
|
||
|
|
end case;
|
||
|
|
when HDMI =>
|
||
|
|
if Port_Cfg.Mode.Dotclock in HDMI_Clock_Range and
|
||
|
|
(Port_Cfg.Mode.Dotclock * 99 / 100 < Clock_Gap'First or
|
||
|
|
Port_Cfg.Mode.Dotclock * 101 / 100 > Clock_Gap'Last)
|
||
|
|
then
|
||
|
|
Calculate_Clock_Parameters
|
||
|
|
(Target_Dotclock => Port_Cfg.Mode.Dotclock,
|
||
|
|
Best_Clock => Clock,
|
||
|
|
Valid => Success);
|
||
|
|
else
|
||
|
|
Success := False;
|
||
|
|
pragma Debug (Debug.Put_Line
|
||
|
|
("Mode's dotclock is out of range."));
|
||
|
|
end if;
|
||
|
|
when others =>
|
||
|
|
Success := False;
|
||
|
|
pragma Debug (Debug.Put_Line ("Invalid display type!"));
|
||
|
|
end case;
|
||
|
|
end if;
|
||
|
|
|
||
|
|
if Success then
|
||
|
|
DDI_Phy.Pre_PLL (Port_Cfg);
|
||
|
|
Program_DPLL (PLL, Clock);
|
||
|
|
end if;
|
||
|
|
end Alloc;
|
||
|
|
|
||
|
|
procedure Free (PLL : T) is
|
||
|
|
begin
|
||
|
|
if PLL in Valid_PLLs then
|
||
|
|
Unset_Mask (PORT (PLL).PLL_ENABLE, PORT_PLL_ENABLE);
|
||
|
|
end if;
|
||
|
|
end Free;
|
||
|
|
|
||
|
|
procedure All_Off is
|
||
|
|
begin
|
||
|
|
pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
|
||
|
|
|
||
|
|
for PLL in Valid_PLLs loop
|
||
|
|
Free (PLL);
|
||
|
|
end loop;
|
||
|
|
end All_Off;
|
||
|
|
|
||
|
|
end HW.GFX.GMA.PLLs;
|