379 lines
15 KiB
Ada
379 lines
15 KiB
Ada
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--
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-- Copyright (C) 2015-2016 secunet Security Networks AG
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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with HW.GFX.GMA.Config;
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with HW.Debug;
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with GNAT.Source_Info;
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package body HW.GFX.GMA.Panel
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with
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Refined_State =>
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(Panel_State =>
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(Delays_US, Power_Cycle_Timer, Power_Up_Timer))
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is
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type Delays_Enum is
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(Power_Up_Delay,
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Power_Up_To_BL_On,
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Power_Down_Delay,
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BL_Off_To_Power_Down,
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Power_Cycle_Delay);
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type Panel_Power_Delays is array (Delays_Enum) of Natural;
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Default_EDP_Delays_US : constant Panel_Power_Delays := Panel_Power_Delays'
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(Power_Up_Delay => 210_000,
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Power_Up_To_BL_On => 50_000,
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Power_Down_Delay => 500_000,
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BL_Off_To_Power_Down => 50_000,
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Power_Cycle_Delay => 510_000);
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Delays_US : Panel_Power_Delays;
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----------------------------------------------------------------------------
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-- And here the mess starts: We have this pretty hardware power sequencer
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-- that should ensure the panel's timing constraints are satisfied. But
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-- (at least on some generations) it doesn't do it's job. On Haswell, it
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-- seems to ignore the Power_Cycle_Delay, so we ensure the delay in soft-
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-- ware. On at least Ivy Bridge and Broadwell Power_Up_Delay is ignored.
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--
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-- If we ever do all delays in software, there are two ways: Either confi-
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-- gure the hardware to zero delays or wait for both the software timeout
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-- and the hardware power sequencer. The latter option would be less error
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-- prone, as the hardware might just don't work as expected.
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Power_Cycle_Timer : Time.T;
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Power_Up_Timer : Time.T;
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----------------------------------------------------------------------------
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function Div_Round_Up32 (Num : Natural; Denom : Positive) return Word32 is
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((Word32 (Num) + Word32 (Denom) - 1) / Word32 (Denom));
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PCH_PP_STATUS_ENABLED : constant := 16#00_0001# * 2 ** 31;
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PCH_PP_STATUS_REQUIRE_ASSET : constant := 16#00_0001# * 2 ** 30;
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PCH_PP_STATUS_PWR_SEQ_PROGRESS_MASK : constant := 16#00_0003# * 2 ** 28;
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PCH_PP_STATUS_PWR_SEQ_PROGRESS_NONE : constant := 16#00_0000# * 2 ** 28;
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PCH_PP_STATUS_PWR_SEQ_PROGRESS_UP : constant := 16#00_0001# * 2 ** 28;
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PCH_PP_STATUS_PWR_SEQ_PROGRESS_DOWN : constant := 16#00_0002# * 2 ** 28;
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PCH_PP_STATUS_PWR_CYC_DELAY_ACTIVE : constant := 16#00_0001# * 2 ** 27;
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PCH_PP_CONTROL_WRITE_PROTECT_MASK : constant := 16#00_ffff# * 2 ** 16;
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PCH_PP_CONTROL_WRITE_PROTECT_KEY : constant := 16#00_abcd# * 2 ** 16;
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PCH_PP_CONTROL_VDD_OVERRIDE : constant := 16#00_0001# * 2 ** 3;
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PCH_PP_CONTROL_BACKLIGHT_ENABLE : constant := 16#00_0001# * 2 ** 2;
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PCH_PP_CONTROL_POWER_DOWN_ON_RESET : constant := 16#00_0001# * 2 ** 1;
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PCH_PP_CONTROL_TARGET_ON : constant := 16#00_0001# * 2 ** 0;
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PCH_PP_ON_DELAYS_PORT_SELECT_MASK : constant := 16#00_0003# * 2 ** 30;
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PCH_PP_ON_DELAYS_PORT_SELECT_LVDS : constant := 16#00_0000# * 2 ** 30;
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PCH_PP_ON_DELAYS_PORT_SELECT_DP_A : constant := 16#00_0001# * 2 ** 30;
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PCH_PP_ON_DELAYS_PORT_SELECT_DP_C : constant := 16#00_0002# * 2 ** 30;
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PCH_PP_ON_DELAYS_PORT_SELECT_DP_D : constant := 16#00_0003# * 2 ** 30;
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PCH_PP_ON_DELAYS_PWR_UP_MASK : constant := 16#00_1fff# * 2 ** 16;
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PCH_PP_ON_DELAYS_PWR_UP_BL_ON_MASK : constant := 16#00_1fff# * 2 ** 0;
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type PP_Regs is record
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STATUS : Registers.Registers_Index;
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CONTROL : Registers.Registers_Index;
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ON_DELAYS : Registers.Registers_Index;
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OFF_DELAYS : Registers.Registers_Index;
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DIVISOR : Registers.Registers_Index;
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end record;
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Panel_PP_Regs : constant PP_Regs := (if Config.Has_PCH_Panel_Power then
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(STATUS => Registers.PCH_PP_STATUS,
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CONTROL => Registers.PCH_PP_CONTROL,
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ON_DELAYS => Registers.PCH_PP_ON_DELAYS,
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OFF_DELAYS => Registers.PCH_PP_OFF_DELAYS,
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DIVISOR => Registers.PCH_PP_DIVISOR)
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else
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(STATUS => Registers.GMCH_PP_STATUS,
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CONTROL => Registers.GMCH_PP_CONTROL,
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ON_DELAYS => Registers.GMCH_PP_ON_DELAYS,
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OFF_DELAYS => Registers.GMCH_PP_OFF_DELAYS,
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DIVISOR => Registers.GMCH_PP_DIVISOR));
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function PCH_PP_ON_DELAYS_PWR_UP (US : Natural) return Word32 is
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begin
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return Shift_Left (Div_Round_Up32 (US, 100), 16);
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end PCH_PP_ON_DELAYS_PWR_UP;
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function PCH_PP_ON_DELAYS_PWR_UP_BL_ON (US : Natural) return Word32 is
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begin
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return Div_Round_Up32 (US, 100);
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end PCH_PP_ON_DELAYS_PWR_UP_BL_ON;
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PCH_PP_OFF_DELAYS_PWR_DOWN_MASK : constant := 16#1fff# * 2 ** 16;
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PCH_PP_OFF_DELAYS_BL_OFF_PWR_DOWN_MASK : constant := 16#1fff# * 2 ** 0;
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function PCH_PP_OFF_DELAYS_PWR_DOWN (US : Natural) return Word32 is
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begin
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return Shift_Left (Div_Round_Up32 (US, 100), 16);
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end PCH_PP_OFF_DELAYS_PWR_DOWN;
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function PCH_PP_OFF_DELAYS_BL_OFF_PWR_DOWN (US : Natural) return Word32 is
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begin
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return Div_Round_Up32 (US, 100);
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end PCH_PP_OFF_DELAYS_BL_OFF_PWR_DOWN;
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PCH_PP_DIVISOR_REF_DIVIDER_MASK : constant := 16#ff_ffff# * 2 ** 8;
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PCH_PP_DIVISOR_PWR_CYC_DELAY_MASK : constant := 16#00_001f# * 2 ** 0;
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function PCH_PP_DIVISOR_PWR_CYC_DELAY (US : Natural) return Word32 is
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begin
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return Div_Round_Up32 (US, 100_000) + 1;
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end PCH_PP_DIVISOR_PWR_CYC_DELAY;
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CPU_BLC_PWM_CTL_ENABLE : constant := 16#00_0001# * 2 ** 31;
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CPU_BLC_PWM_CTL_PIPE_SELECT_MASK : constant := 16#00_0003# * 2 ** 29;
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CPU_BLC_PWM_CTL_PIPE_SELECT_PIPE_A : constant := 16#00_0000# * 2 ** 29;
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CPU_BLC_PWM_CTL_PIPE_SELECT_PIPE_B : constant := 16#00_0001# * 2 ** 29;
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CPU_BLC_PWM_CTL_PIPE_SELECT_PIPE_C : constant := 16#00_0002# * 2 ** 29;
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CPU_BLC_PWM_DATA_BL_DUTY_CYC_MASK : constant := 16#00_ffff# * 2 ** 0;
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PCH_BLC_PWM_CTL1_ENABLE : constant := 16#00_0001# * 2 ** 31;
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PCH_BLC_PWM_CTL1_BL_POLARITY_MASK : constant := 16#00_0001# * 2 ** 29;
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PCH_BLC_PWM_CTL1_PHASE_IN_INTR_STAT : constant := 16#00_0001# * 2 ** 26;
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PCH_BLC_PWM_CTL1_PHASE_IN_ENABLE : constant := 16#00_0001# * 2 ** 25;
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PCH_BLC_PWM_CTL1_PHASE_IN_INTR_EN : constant := 16#00_0001# * 2 ** 24;
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PCH_BLC_PWM_CTL1_PHASE_IN_TIME_BASE : constant := 16#00_00ff# * 2 ** 16;
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PCH_BLC_PWM_CTL1_PHASE_IN_COUNT : constant := 16#00_00ff# * 2 ** 8;
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PCH_BLC_PWM_CTL1_PHASE_IN_INCREMENT : constant := 16#00_00ff# * 2 ** 0;
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PCH_BLC_PWM_CTL2_BL_MOD_FREQ_MASK : constant := 16#00_ffff# * 2 ** 16;
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PCH_BLC_PWM_CTL2_BL_DUTY_CYC_MASK : constant := 16#00_ffff# * 2 ** 0;
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----------------------------------------------------------------------------
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procedure Static_Init
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with
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Refined_Global =>
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(Output => (Power_Cycle_Timer, Power_Up_Timer, Delays_US),
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Input => (Time.State))
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is
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begin
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Power_Cycle_Timer := Time.Now;
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Power_Up_Timer := Power_Cycle_Timer;
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Delays_US := Default_EDP_Delays_US;
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end Static_Init;
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----------------------------------------------------------------------------
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procedure Check_PP_Delays
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(Delays : in out Panel_Power_Delays;
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Override : in out Boolean) is
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begin
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for D in Delays_Enum loop
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if Delays (D) = 0 then
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Delays (D) := Default_EDP_Delays_US (D);
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Override := True;
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end if;
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end loop;
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end Check_PP_Delays;
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procedure Setup_PP_Sequencer (Default_Delays : Boolean := False)
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is
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Power_Delay, Port_Select : Word32;
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Override_Delays : Boolean := False;
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begin
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pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
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Static_Init;
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if Default_Delays then
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Override_Delays := True;
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else
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Registers.Read (Panel_PP_Regs.ON_DELAYS, Power_Delay);
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Delays_US (Power_Up_Delay) := 100 * Natural
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(Shift_Right (Power_Delay and PCH_PP_ON_DELAYS_PWR_UP_MASK, 16));
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Delays_US (Power_Up_To_BL_On) := 100 * Natural
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(Power_Delay and PCH_PP_ON_DELAYS_PWR_UP_BL_ON_MASK);
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Registers.Read (Panel_PP_Regs.OFF_DELAYS, Power_Delay);
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Delays_US (Power_Down_Delay) := 100 * Natural
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(Shift_Right (Power_Delay and PCH_PP_OFF_DELAYS_PWR_DOWN_MASK, 16));
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Delays_US (BL_Off_To_Power_Down) := 100 * Natural
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(Power_Delay and PCH_PP_OFF_DELAYS_BL_OFF_PWR_DOWN_MASK);
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Registers.Read (Panel_PP_Regs.DIVISOR, Power_Delay);
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if (Power_Delay and PCH_PP_DIVISOR_PWR_CYC_DELAY_MASK) > 1 then
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Delays_US (Power_Cycle_Delay) := 100_000 * (Natural
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(Power_Delay and PCH_PP_DIVISOR_PWR_CYC_DELAY_MASK) - 1);
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end if;
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Check_PP_Delays (Delays_US, Override_Delays);
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end if;
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if Override_Delays then
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if Config.Has_PP_Port_Select then
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if Config.Internal_Is_EDP then
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Port_Select := PCH_PP_ON_DELAYS_PORT_SELECT_DP_A;
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else
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Port_Select := PCH_PP_ON_DELAYS_PORT_SELECT_LVDS;
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end if;
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else
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Port_Select := 0;
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end if;
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-- Force power-up to backlight-on delay to 100us as recommended by PRM.
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Registers.Unset_And_Set_Mask
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(Register => Panel_PP_Regs.ON_DELAYS,
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Mask_Unset => PCH_PP_ON_DELAYS_PORT_SELECT_MASK or
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PCH_PP_ON_DELAYS_PWR_UP_MASK or
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PCH_PP_ON_DELAYS_PWR_UP_BL_ON_MASK,
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Mask_Set => Port_Select or
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PCH_PP_ON_DELAYS_PWR_UP (Delays_US (Power_Up_Delay))
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or PCH_PP_ON_DELAYS_PWR_UP_BL_ON (100));
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Registers.Unset_And_Set_Mask
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(Register => Panel_PP_Regs.OFF_DELAYS,
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Mask_Unset => PCH_PP_OFF_DELAYS_PWR_DOWN_MASK or
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PCH_PP_OFF_DELAYS_BL_OFF_PWR_DOWN_MASK,
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Mask_Set => PCH_PP_OFF_DELAYS_PWR_DOWN
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(Delays_US (Power_Down_Delay)) or
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PCH_PP_OFF_DELAYS_BL_OFF_PWR_DOWN
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(Delays_US (BL_Off_To_Power_Down)));
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Registers.Unset_And_Set_Mask
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(Register => Panel_PP_Regs.DIVISOR,
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Mask_Unset => PCH_PP_DIVISOR_PWR_CYC_DELAY_MASK,
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Mask_Set => PCH_PP_DIVISOR_PWR_CYC_DELAY
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(Delays_US (Power_Cycle_Delay)));
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end if;
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if Config.Has_PP_Write_Protection then
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Registers.Unset_And_Set_Mask
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(Register => Panel_PP_Regs.CONTROL,
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Mask_Unset => PCH_PP_CONTROL_WRITE_PROTECT_MASK,
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Mask_Set => PCH_PP_CONTROL_WRITE_PROTECT_KEY or
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PCH_PP_CONTROL_POWER_DOWN_ON_RESET);
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else
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Registers.Set_Mask
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(Register => Panel_PP_Regs.CONTROL,
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Mask => PCH_PP_CONTROL_POWER_DOWN_ON_RESET);
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end if;
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end Setup_PP_Sequencer;
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----------------------------------------------------------------------------
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procedure VDD_Override is
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begin
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pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
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-- Yeah, We could do, what we are supposed to do here. But OTOH, we
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-- are should wait for the full Power Up Delay, which we would have
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-- to do later again. And just powering on the display seems to work
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-- too. Also this function vanished on newer hardware.
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On;
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end VDD_Override;
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procedure On (Wait : Boolean := True)
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is
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Was_On : Boolean;
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begin
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pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
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Registers.Is_Set_Mask (Panel_PP_Regs.CONTROL, PCH_PP_CONTROL_TARGET_ON, Was_On);
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if not Was_On then
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Time.Delay_Until (Power_Cycle_Timer);
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end if;
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Registers.Set_Mask (Panel_PP_Regs.CONTROL, PCH_PP_CONTROL_TARGET_ON);
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if not Was_On then
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Power_Up_Timer := Time.US_From_Now (Delays_US (Power_Up_Delay));
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end if;
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if Wait then
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Wait_On;
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end if;
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end On;
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procedure Wait_On is
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begin
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pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
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Time.Delay_Until (Power_Up_Timer);
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Registers.Wait_Unset_Mask
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(Register => Panel_PP_Regs.STATUS,
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Mask => PCH_PP_STATUS_PWR_SEQ_PROGRESS_MASK,
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TOut_MS => 300);
|
||
|
|
|
||
|
|
Registers.Unset_Mask (Panel_PP_Regs.CONTROL, PCH_PP_CONTROL_VDD_OVERRIDE);
|
||
|
|
end Wait_On;
|
||
|
|
|
||
|
|
procedure Off
|
||
|
|
is
|
||
|
|
Was_On : Boolean;
|
||
|
|
begin
|
||
|
|
pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
|
||
|
|
|
||
|
|
Registers.Is_Set_Mask (Panel_PP_Regs.CONTROL, PCH_PP_CONTROL_TARGET_ON, Was_On);
|
||
|
|
Registers.Unset_Mask
|
||
|
|
(Register => Panel_PP_Regs.CONTROL,
|
||
|
|
Mask => PCH_PP_CONTROL_TARGET_ON or
|
||
|
|
PCH_PP_CONTROL_VDD_OVERRIDE);
|
||
|
|
if Was_On then
|
||
|
|
Time.U_Delay (Delays_US (Power_Down_Delay));
|
||
|
|
end if;
|
||
|
|
Registers.Wait_Unset_Mask
|
||
|
|
(Register => Panel_PP_Regs.STATUS,
|
||
|
|
Mask => PCH_PP_STATUS_PWR_SEQ_PROGRESS_MASK,
|
||
|
|
TOut_MS => 600);
|
||
|
|
if Was_On then
|
||
|
|
Power_Cycle_Timer := Time.US_From_Now (Delays_US (Power_Cycle_Delay));
|
||
|
|
end if;
|
||
|
|
end Off;
|
||
|
|
|
||
|
|
----------------------------------------------------------------------------
|
||
|
|
|
||
|
|
procedure Backlight_On is
|
||
|
|
begin
|
||
|
|
pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
|
||
|
|
|
||
|
|
Registers.Set_Mask
|
||
|
|
(Register => Panel_PP_Regs.CONTROL,
|
||
|
|
Mask => PCH_PP_CONTROL_BACKLIGHT_ENABLE);
|
||
|
|
end Backlight_On;
|
||
|
|
|
||
|
|
procedure Backlight_Off is
|
||
|
|
begin
|
||
|
|
pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
|
||
|
|
|
||
|
|
Registers.Unset_Mask
|
||
|
|
(Register => Panel_PP_Regs.CONTROL,
|
||
|
|
Mask => PCH_PP_CONTROL_BACKLIGHT_ENABLE);
|
||
|
|
end Backlight_Off;
|
||
|
|
|
||
|
|
procedure Set_Backlight (Level : Word16) is
|
||
|
|
begin
|
||
|
|
pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
|
||
|
|
|
||
|
|
Registers.Unset_And_Set_Mask
|
||
|
|
(Register => Registers.BLC_PWM_CPU_CTL,
|
||
|
|
Mask_Unset => CPU_BLC_PWM_DATA_BL_DUTY_CYC_MASK,
|
||
|
|
Mask_Set => Word32 (Level));
|
||
|
|
end Set_Backlight;
|
||
|
|
|
||
|
|
procedure Get_Max_Backlight (Level : out Word16)
|
||
|
|
is
|
||
|
|
Reg : Word32;
|
||
|
|
begin
|
||
|
|
pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
|
||
|
|
|
||
|
|
Registers.Read (Registers.BLC_PWM_PCH_CTL2, Reg);
|
||
|
|
Level := Word16
|
||
|
|
(Shift_Right (Reg and PCH_BLC_PWM_CTL2_BL_MOD_FREQ_MASK, 16));
|
||
|
|
end Get_Max_Backlight;
|
||
|
|
|
||
|
|
end HW.GFX.GMA.Panel;
|