38 lines
1.2 KiB
Markdown
38 lines
1.2 KiB
Markdown
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Ariane FPGA SoC Platform
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==========================
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Ariane is a 6-stage, single issue, in-order CPU which implements the 64-bit RISC-V instruction set.
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The Ariane FPGA development platform is based on FPGA FPGA SoC(which currently supports only Genesys 2 board) and is capable
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of running Linux.
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The FPGA SoC currently contains the following peripherals:
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- DDR3 memory controller
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- SPI controller to conncet to an SDCard
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- Ethernet controller
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- JTAG port (see debugging section below)
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- Bootrom containing zero stage bootloader and device tree.
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To build platform specific library and firmwares, provide the
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*PLATFORM=ariane-fpga* parameter to the top level `make` command.
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Platform Options
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----------------
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The *Ariane FPGA* platform does not have any platform-specific
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options.
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Building Ariane FPGA Platform
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-----------------------------
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**Linux Kernel Payload**
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```
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make PLATFORM=ariane-fpga FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image
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```
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Booting Ariane FPGA Platform
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-----------------------------
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**Linux Kernel Payload**
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As Linux kernel image is embedded in the OpenSBI firmware binary, Ariane will directly
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boot into Linux directly after powered on.
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