101 lines
3.5 KiB
Markdown
101 lines
3.5 KiB
Markdown
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# SiFive HiFive Unleashed
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This page describes how to run coreboot on the [HiFive Unleashed] development
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board from [SiFive], the first RISC-V board on the market with enough resources
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to run a multiuser operating system.
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For general setup instructions, please refer to the [Getting Started Guide].
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## TODO
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The following things are still missing from this coreboot port:
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- Support running romstage from flash (fix stack) to support boot mode 1
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- Starting the U54 cores
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- FU540 PIN configuration and GPIO access macros
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- Provide serial number to payload (e.g. in device tree)
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- Implement instruction emulation
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- Support for booting Linux on RISC-V
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- SMP support in trap handler
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## Configuration
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Run `make menuconfig` and select _SiFive_/_HiFive Unleashed_ in the _Mainboard_
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menu.
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### Boot modes
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A total of 16 boot modes can be configured using the switches labeled `MSEL0`
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through `MSEL3`. The most important ones are as follows:
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- **MSEL=1**: Jump directly into the SPI flash, bypassing ROM1
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- **MSEL=11**: Load FSBL from SD-card
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- **MSEL=15**: Default boot mode; Load FSBL/coreboot from a GPT partition on
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SPI flash
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## Flashing coreboot
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The HiFive Unleashed has an 32 MiB SPI flash (**ISSI IS25WP256D**), that can be
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programmed from within Linux running on the board, via USB/JTAG, or directly
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with an SPI programmer.
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### Internal programming
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The SPI flash can be accessed as `/dev/mtd0` from Linux.
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### USB/JTAG
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To program the flash via USB/JTAG, connect the USB port to a computer. If the
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board is powered on, two new serial ports, for example `/dev/ttyUSB0` and
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`/dev/ttyUSB1` will appear. The first is JTAG, and the second is connected to
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the SoC's UART.
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- Download and build the [RISC-V fork of OpenOCD].
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- Download the [OpenOCD script] for Freedom Unleashed.
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- Start OpenOCD with `openocd -f openocd.cfg`
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- Connect to OpenOCD's command interface (via telnet) and enter the line
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marked with `> `:
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```
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> flash write_image erase unlock build/coreboot.rom 0x20000000
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auto erase enabled
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auto unlock enabled
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wrote 33554432 bytes from file build/coreboot.rom in 1524.943848s (21.488 KiB/s)
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```
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Note that programming the whole flash with OpenOCD isn't fast. In this
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example it took just over 25 minutes. This process can be sped up
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considerably by building/flashing a smaller image; OpenOCD does not check if
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the image and the flash have the same size.
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### External programming
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External programming with an SPI adapter and [flashrom] may work, but has not
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been tested. Please study the [schematics] before going this route.
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## Error codes
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The zeroth-stage bootloader (ZSBL) in ROM1 can print error codes on the serial
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console in certain situations.
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```
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// Error codes are formatted as follows:
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// [63:60] [59:56] [55:0]
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// bootstage trap errorcode
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// If trap == 1, then errorcode is actually the mcause register with the
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// interrupt bit shifted to bit 55.
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```
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(--- from the [SiFive forum](https://forums.sifive.com/t/loading-fsbl-from-sd/1156/4))
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[HiFive Unleashed]: https://www.crowdsupply.com/sifive/hifive-unleashed
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[SiFive]: https://www.sifive.com/
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[Getting Started Guide]: https://sifive.cdn.prismic.io/sifive%2Ffa3a584a-a02f-4fda-b758-a2def05f49f9_hifive-unleashed-getting-started-guide-v1p1.pdf
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[RISC-V fork of OpenOCD]: https://github.com/riscv/riscv-openocd
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[OpenOCD script]: https://github.com/sifive/freedom-u-sdk/blob/057a47f657fa33e2c60df7f183884a68e90381cc/bsp/env/freedom-u500-unleashed/openocd.cfg
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[flashrom]: https://flashrom.org/Flashrom
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[schematics]: https://sifive.cdn.prismic.io/sifive%2Ff7173056-bf37-4407-87cb-d5ab76abf61a_hifive-unleashed-a00-schematics.pdf
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