118 lines
4.3 KiB
Markdown
118 lines
4.3 KiB
Markdown
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# Intel Trusted Execution Technology
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Intel TXT allows
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1. Attestation of the authenticity of a platform and its operating system.
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2. Assuring that an authentic operating system starts in a
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trusted environment, which can then be considered trusted.
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3. Providing of a trusted operating system with additional
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security capabilities not available to an unproven one.
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Intel TXT requirements:
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1. Intel TXT requires a **TPM** to measure parts of the firmware before it's
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run on the BSP.
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2. Intel TXT requires signed **Authenticated Code Modules** ([ACM]s), provided
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by Intel.
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3. Intel TXT requires **CPU and Chipset** support (supported since
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Intel Core 2 Duo/ICH9).
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## Authenticated Code Modules
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The ACMs are Intel digitally signed modules that contain code to be run
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before the traditional x86 CPU reset vector.
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More details can be found here: [Intel ACM].
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## Modified bootflow with Intel TXT
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With Intel TXT the first instruction executed on the BSP isn't the
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*reset vector*, but the [Intel ACM].
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It initializes the TPM and measures parts of the firmware, the IBB.
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### Marking the Initial Boot Block
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Individual files in the CBFS can be marked as IBB.
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More details can be found in the [Intel TXT IBB] chapter.
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### Measurements
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The IBBs (Initial Boot Blocks) are measured into TPM's PCR0 by the BIOS [ACM]
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before the CPU reset vector is executed. To indentify the regions that need
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to be measured, the [FIT] contains one ore multiple *Type 7* entries, that
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point to the IBBs.
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### Authentication
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After the IBBs have been measured, the ACM decides if the boot firmware is
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trusted. There exists two validation modes:
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1. HASH Autopromotion
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* Uses a known good HASH stored in TPM NVRAM
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* Doesn't allow to boot a fallback IBB
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2. Signed BIOS policy
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* Uses a signed policy stored in flash containing multiple HASHes
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* The public key HASH of BIOS policy is burned into TPM by manufacturer
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* Can be updated by firmware
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* Allows to boot a fallback IBB
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At the moment only *Autopromotion mode* is implemented and tested well.
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In the next step the ACM terminates and the regular x86 CPU reset vector
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is being executed on the BSP.
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### Protecting Secrets in Memory
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Intel TXT sets the `Secrets in Memory` bit, whenever the launch of the SINIT
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ACM was successful.
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The bit is reset when leaving the *MLE* by a regular shutdown or by removing
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the CMOS battery.
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When `Secrets in Memory` bit is set and the IBB isn't trusted, the memory
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controller won't be unlocked, resulting in a platform that cannot access DRAM.
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When `Secrets in Memory` bit is set and the IBB is trusted, the memory
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controller will be unlocked, and it's the responsibility of the firmware to
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[clear all DRAM] and wipe any secrets of the MLE.
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The platform will be reset after all DRAM has been wiped and will boot
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with the `Secrets in Memory` bit cleared.
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### Configuring protected regions for SINIT ACM
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The memory regions used by the SINIT ACM need to be prepared and protected
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against DMA attacks.
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The SINIT ACM as well as the SINIT handoff data are placed in memory.
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### Locking TXT register
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As last step the TXT registers are locked.
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Whenever the SINIT ACM is invoked, it verifies that the hardware is in the
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correct state. If it's not the SINIT ACM will reset the platform.
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## For developers
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### Configuring Intel TXT in Kconfig
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Enable ``INTEL_TXT`` and set the following:
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``INTEL_TXT_BIOSACM_FILE`` to the path of the BIOS ACM provided by Intel
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``INTEL_TXT_SINITACM_FILE`` to the path of the SINIT ACM provided by Intel
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### Print TXT status as early as possible
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Add platform code to print the TXT status as early as possible, as the register
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is cleared on cold reset.
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## References
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More information can be found here:
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* [Intel TXT Software Development Guide]
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* [Intel TXT enabling]
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* [FIT]
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* [Intel TXT Lab Handout]
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[Intel TXT IBB]: txt_ibb.md
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[FIT]: ../../soc/intel/fit.md
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[Intel ACM]: acm.md
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[ACM]: acm.md
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[FIT table]: ../../soc/intel/fit.md
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[clear all DRAM]: ../memory_clearing.md
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[Intel TXT Lab Handout]: https://downloadmirror.intel.com/18931/eng/Intel%20TXT%20LAB%20Handout.pdf
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[Intel TXT Software Development Guide]: https://www.intel.com/content/dam/www/public/us/en/documents/guides/intel-txt-software-development-guide.pdf
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[Intel TXT enabling]: https://www.intel.com/content/dam/www/public/us/en/documents/guides/txt-enabling-guide.pdf
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