77 lines
2.9 KiB
Markdown
77 lines
2.9 KiB
Markdown
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# Lenovo Ivy Bridge series
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## Flashing coreboot
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```eval_rst
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+---------------------+--------------------------------+
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| Type | Value |
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+=====================+================================+
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| Socketed flash | no |
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+---------------------+--------------------------------+
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| Size | 8 MiB + 4MiB |
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+---------------------+--------------------------------+
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| In circuit flashing | Yes |
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+---------------------+--------------------------------+
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| Package | SOIC-8 |
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+---------------------+--------------------------------+
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| Write protection | No |
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+---------------------+--------------------------------+
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| Dual BIOS feature | No |
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+---------------------+--------------------------------+
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| Internal flashing | Yes |
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+---------------------+--------------------------------+
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```
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## Installation instructions
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* Update the EC firmware, as there's no support for EC updates in coreboot.
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* Do **NOT** accidently swap pins or power on the board while a SPI flasher
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is connected. It will permanently brick your device.
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* It's recommended to only flash the BIOS region. In that case you don't
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need to extract blobs from vendor firmware.
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If you want to flash the whole chip, you need blobs when building
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coreboot.
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* The *Flash layout* shows that by default 7MiB of space are available for
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the use with coreboot.
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* In that case you only want to use a part of the BIOS region that must not
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exceed 4MiB in size, which means CONFIG_CBFS_SIZE must be smaller than 4MiB.
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* ROM chip size should be set to 12MiB.
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```eval_rst
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Please also have a look at :doc:`../../flash_tutorial/index`.
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```
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## Splitting the coreboot.rom
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To split the coreboot.rom into two images (one for the 8MiB and one for the
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4 MiB flash IC), run the following commands:
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```bash
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dd of=top.rom bs=1M if=build/coreboot.rom skip=8
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dd of=bottom.rom bs=1M if=build/coreboot.rom count=8
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```
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That gives one ROM for each flash IC, where *top.rom* is the upper part of the
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flash image, that resides on the 4 MiB flash and *bottom.rom* is the lower part
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of the flash image, that resides on the 8 MiB flash.
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## Dumping a full ROM
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If you flash externally you need to read both flash chips to get two images
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(one for the 8MiB and one for the 4 MiB flash IC), and then run the following
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command to concatenate the files:
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```bash
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cat bottom.rom top.rom > firmware.rom
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```
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## Flash layout
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There's one 8MiB and one 4 MiB flash which contains IFD, GBE, ME and
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BIOS region. These two flash ICs appear as a single 12MiB when flashing
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internally.
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On Lenovo's UEFI the EC firmware update is placed at the start of the BIOS
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region. The update is then written into the EC once.
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![][fl]
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[fl]: flashlayout_xx30.svg
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