206 lines
5.9 KiB
C
206 lines
5.9 KiB
C
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/*
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* Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef BSEC_H
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#define BSEC_H
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#include <stdbool.h>
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#include <stdint.h>
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#include <lib/utils_def.h>
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/*
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* IP configuration
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*/
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#define BSEC_OTP_MASK GENMASK(4, 0)
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#define BSEC_OTP_BANK_SHIFT 5
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#define BSEC_TIMEOUT_VALUE 0xFFFF
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#define ADDR_LOWER_OTP_PERLOCK_SHIFT 0x03
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#define DATA_LOWER_OTP_PERLOCK_BIT 0x03U /* 2 significants bits are used */
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#define DATA_LOWER_OTP_PERLOCK_MASK GENMASK(2, 0)
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#define ADDR_UPPER_OTP_PERLOCK_SHIFT 0x04
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#define DATA_UPPER_OTP_PERLOCK_BIT 0x01U /* 1 significants bits are used */
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#define DATA_UPPER_OTP_PERLOCK_MASK GENMASK(3, 0)
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/*
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* Return status
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*/
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#define BSEC_OK 0U
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#define BSEC_ERROR 0xFFFFFFFFU
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#define BSEC_DISTURBED 0xFFFFFFFEU
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#define BSEC_INVALID_PARAM 0xFFFFFFFCU
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#define BSEC_PROG_FAIL 0xFFFFFFFBU
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#define BSEC_LOCK_FAIL 0xFFFFFFFAU
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#define BSEC_WRITE_FAIL 0xFFFFFFF9U
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#define BSEC_SHADOW_FAIL 0xFFFFFFF8U
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#define BSEC_TIMEOUT 0xFFFFFFF7U
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/*
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* BSEC REGISTER OFFSET (base relative)
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*/
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#define BSEC_OTP_CONF_OFF 0x000U
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#define BSEC_OTP_CTRL_OFF 0x004U
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#define BSEC_OTP_WRDATA_OFF 0x008U
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#define BSEC_OTP_STATUS_OFF 0x00CU
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#define BSEC_OTP_LOCK_OFF 0x010U
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#define BSEC_DEN_OFF 0x014U
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#define BSEC_DISTURBED_OFF 0x01CU
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#define BSEC_DISTURBED1_OFF 0x020U
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#define BSEC_DISTURBED2_OFF 0x024U
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#define BSEC_ERROR_OFF 0x034U
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#define BSEC_ERROR1_OFF 0x038U
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#define BSEC_ERROR2_OFF 0x03CU
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#define BSEC_WRLOCK_OFF 0x04CU /* Safmem permanent lock */
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#define BSEC_WRLOCK1_OFF 0x050U
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#define BSEC_WRLOCK2_OFF 0x054U
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#define BSEC_SPLOCK_OFF 0x064U /* Program safmem sticky lock */
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#define BSEC_SPLOCK1_OFF 0x068U
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#define BSEC_SPLOCK2_OFF 0x06CU
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#define BSEC_SWLOCK_OFF 0x07CU /* Write in OTP sticky lock */
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#define BSEC_SWLOCK1_OFF 0x080U
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#define BSEC_SWLOCK2_OFF 0x084U
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#define BSEC_SRLOCK_OFF 0x094U /* Shadowing sticky lock */
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#define BSEC_SRLOCK1_OFF 0x098U
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#define BSEC_SRLOCK2_OFF 0x09CU
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#define BSEC_JTAG_IN_OFF 0x0ACU
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#define BSEC_JTAG_OUT_OFF 0x0B0U
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#define BSEC_SCRATCH_OFF 0x0B4U
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#define BSEC_OTP_DATA_OFF 0x200U
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#define BSEC_IPHW_CFG_OFF 0xFF0U
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#define BSEC_IPVR_OFF 0xFF4U
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#define BSEC_IP_ID_OFF 0xFF8U
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#define BSEC_IP_MAGIC_ID_OFF 0xFFCU
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/*
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* BSEC_CONFIGURATION Register
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*/
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#define BSEC_CONF_POWER_UP_MASK BIT(0)
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#define BSEC_CONF_POWER_UP_SHIFT 0
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#define BSEC_CONF_FRQ_MASK GENMASK(2, 1)
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#define BSEC_CONF_FRQ_SHIFT 1
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#define BSEC_CONF_PRG_WIDTH_MASK GENMASK(6, 3)
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#define BSEC_CONF_PRG_WIDTH_SHIFT 3
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#define BSEC_CONF_TREAD_MASK GENMASK(8, 7)
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#define BSEC_CONF_TREAD_SHIFT 7
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/*
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* BSEC_CONTROL Register
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*/
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#define BSEC_READ 0x000U
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#define BSEC_WRITE 0x100U
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#define BSEC_LOCK 0x200U
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/*
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* BSEC_OTP_LOCK register
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*/
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#define UPPER_OTP_LOCK_MASK BIT(0)
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#define UPPER_OTP_LOCK_SHIFT 0
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#define DENREG_LOCK_MASK BIT(2)
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#define DENREG_LOCK_SHIFT 2
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#define GPLOCK_LOCK_MASK BIT(4)
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#define GPLOCK_LOCK_SHIFT 4
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/*
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* BSEC_OTP_STATUS Register
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*/
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#define BSEC_MODE_STATUS_MASK GENMASK(2, 0)
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#define BSEC_MODE_BUSY_MASK BIT(3)
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#define BSEC_MODE_PROGFAIL_MASK BIT(4)
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#define BSEC_MODE_PWR_MASK BIT(5)
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#define BSEC_MODE_BIST1_LOCK_MASK BIT(6)
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#define BSEC_MODE_BIST2_LOCK_MASK BIT(7)
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/* OTP MODE*/
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#define BSEC_MODE_OPEN1 0x00
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#define BSEC_MODE_SECURED 0x01
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#define BSEC_MODE_OPEN2 0x02
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#define BSEC_MODE_INVALID 0x04
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/* BSEC_DENABLE Register */
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#define BSEC_HDPEN BIT(4)
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#define BSEC_SPIDEN BIT(5)
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#define BSEC_SPINDEN BIT(6)
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#define BSEC_DBGSWGEN BIT(10)
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#define BSEC_DEN_ALL_MSK GENMASK(10, 0)
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/* BSEC_FENABLE Register */
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#define BSEC_FEN_ALL_MSK GENMASK(14, 0)
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/*
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* OTP Lock services definition
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* Value must corresponding to the bit number in the register
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*/
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#define BSEC_LOCK_UPPER_OTP 0x00
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#define BSEC_LOCK_DEBUG 0x02
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#define BSEC_LOCK_PROGRAM 0x03
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/* Values for struct bsec_config::freq */
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#define FREQ_10_20_MHZ 0x0
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#define FREQ_20_30_MHZ 0x1
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#define FREQ_30_45_MHZ 0x2
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#define FREQ_45_67_MHZ 0x3
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/*
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* Device info structure, providing device-specific functions and a means of
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* adding driver-specific state
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*/
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struct bsec_config {
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uint8_t tread; /* SAFMEM Reading current level default 0 */
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uint8_t pulse_width; /* SAFMEM Programming pulse width default 1 */
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uint8_t freq; /* SAFMEM CLOCK see freq value define
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* default FREQ_45_67_MHZ
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*/
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uint8_t power; /* Power up SAFMEM. 1 power up, 0 power off */
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uint8_t prog_lock; /* Programming Sticky lock
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* 1 programming is locked until next reset
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*/
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uint8_t den_lock; /* Debug enable sticky lock
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* 1 debug enable is locked until next reset
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*/
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uint8_t upper_otp_lock; /* Shadowing of upper OTP sticky lock
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* 1 shadowing of upper OTP is locked
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* until next reset
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*/
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};
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uint32_t bsec_probe(void);
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uint32_t bsec_get_base(void);
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uint32_t bsec_set_config(struct bsec_config *cfg);
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uint32_t bsec_get_config(struct bsec_config *cfg);
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uint32_t bsec_shadow_register(uint32_t otp);
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uint32_t bsec_read_otp(uint32_t *val, uint32_t otp);
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uint32_t bsec_write_otp(uint32_t val, uint32_t otp);
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uint32_t bsec_program_otp(uint32_t val, uint32_t otp);
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uint32_t bsec_permanent_lock_otp(uint32_t otp);
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uint32_t bsec_write_debug_conf(uint32_t val);
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uint32_t bsec_read_debug_conf(void);
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uint32_t bsec_write_feature_conf(uint32_t val);
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uint32_t bsec_read_feature_conf(uint32_t *val);
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uint32_t bsec_get_status(void);
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uint32_t bsec_get_hw_conf(void);
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uint32_t bsec_get_version(void);
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uint32_t bsec_get_id(void);
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uint32_t bsec_get_magic_id(void);
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bool bsec_write_sr_lock(uint32_t otp, uint32_t value);
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bool bsec_read_sr_lock(uint32_t otp);
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bool bsec_write_sw_lock(uint32_t otp, uint32_t value);
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bool bsec_read_sw_lock(uint32_t otp);
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bool bsec_write_sp_lock(uint32_t otp, uint32_t value);
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bool bsec_read_sp_lock(uint32_t otp);
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bool bsec_wr_lock(uint32_t otp);
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uint32_t bsec_otp_lock(uint32_t service, uint32_t value);
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uint32_t bsec_shadow_read_otp(uint32_t *otp_value, uint32_t word);
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uint32_t bsec_check_nsec_access_rights(uint32_t otp);
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#endif /* BSEC_H */
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