94 lines
1.8 KiB
C
94 lines
1.8 KiB
C
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/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdbool.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <lib/el3_runtime/pubsub.h>
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#include <lib/extensions/spe.h>
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static inline void psb_csync(void)
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{
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/*
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* The assembler does not yet understand the psb csync mnemonic
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* so use the equivalent hint instruction.
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*/
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__asm__ volatile("hint #17");
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}
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bool spe_supported(void)
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{
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uint64_t features;
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features = read_id_aa64dfr0_el1() >> ID_AA64DFR0_PMS_SHIFT;
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return (features & ID_AA64DFR0_PMS_MASK) == 1U;
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}
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void spe_enable(bool el2_unused)
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{
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uint64_t v;
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if (!spe_supported())
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return;
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if (el2_unused) {
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/*
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* MDCR_EL2.TPMS (ARM v8.2): Do not trap statistical
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* profiling controls to EL2.
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*
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* MDCR_EL2.E2PB (ARM v8.2): SPE enabled in Non-secure
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* state. Accesses to profiling buffer controls at
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* Non-secure EL1 are not trapped to EL2.
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*/
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v = read_mdcr_el2();
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v &= ~MDCR_EL2_TPMS;
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v |= MDCR_EL2_E2PB(MDCR_EL2_E2PB_EL1);
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write_mdcr_el2(v);
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}
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/*
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* MDCR_EL2.NSPB (ARM v8.2): SPE enabled in Non-secure state
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* and disabled in secure state. Accesses to SPE registers at
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* S-EL1 generate trap exceptions to EL3.
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*/
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v = read_mdcr_el3();
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v |= MDCR_NSPB(MDCR_NSPB_EL1);
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write_mdcr_el3(v);
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}
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void spe_disable(void)
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{
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uint64_t v;
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if (!spe_supported())
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return;
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/* Drain buffered data */
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psb_csync();
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dsbnsh();
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/* Disable profiling buffer */
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v = read_pmblimitr_el1();
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v &= ~(1ULL << 0);
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write_pmblimitr_el1(v);
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isb();
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}
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static void *spe_drain_buffers_hook(const void *arg)
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{
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if (!spe_supported())
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return (void *)-1;
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/* Drain buffered data */
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psb_csync();
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dsbnsh();
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return (void *)0;
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}
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SUBSCRIBE_TO_EVENT(cm_entering_secure_world, spe_drain_buffers_hook);
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